Device and method for computing-in-memory

A computing device, comprising:

• a first plurality of memory elements arranged in a first array extending in a first direction and each including two ends and a current path between the two ends;
• a first conductive line extending along the first array;
• a first plurality of transistors each having a source, a drain and a current path between the source and drain, and a gate, wherein the current path of each of the first plurality of transistors forms a serial combination with the current path of a respective one of the first plurality of memory elements, the serial combination being connected between a first voltage reference point and the first conductive line;
• and
• a first plurality of operational amplifiers (OPAMPs), each having an output end connected to the gate of a respective one of the first plurality of transistors.

A computing device, comprising:

• a first plurality of memory elements arranged in a first array extending in a first direction and each including two ends and a current path between the two ends;
• a first conductive line extending in the first direction;
• a first plurality of transistors each having a source, a drain and a current path between the source and drain, and a gate, the current path of each of the first plurality of transistors forming a serial combination with the current path of a respective one of the first plurality of memory elements the serial combination being switchably connected between a first voltage reference point and the first conductive line;
• a first plurality of amplifiers, each having an output end connected to the gate of a respective one of the first plurality of the transistors;
• a second plurality of memory elements arranged in an array extending in the first direction, each including two ends and a current path between the two ends;
• and
• a second plurality of transistors each having a source, a drain and a current path between the two current-carrying ends, and a gate, wherein the current path of each of the second plurality of transistors forms a serial combination with the current path of a respective one of the second plurality of memory elements, the serial combination being connected between a second voltage reference point and the first conductive line, the output end of each of a second plurality of amplifiers being connected to the gate of a respective one of the second plurality of the transistors, wherein the computing device is configured to charge and discharge the first conductive line, in alternating charging and discharging cycles, by a current through each one of the second plurality of transistors and a current through each one of the first plurality of transistors, respectively.

A method of computing, comprising:

• converting a first plurality of digital input signals, each indicative a respective first number, to a first respective plurality of analog signals, each having an ON-period, the length of which is indicative of the respective first number;
• generating a first plurality of currents, each through a respective one of a first plurality of memory cells, each of which in a respective memory state, each of the first plurality of currents having a magnitude indicative of a combination of a respective one of the first numbers and the state of the respective memory cell;
• generating a first analog signal on a conductive line by charging or discharging the conductive line with the first plurality of currents;
• and
• converting the first analog signal to a first digital output signal.