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US 11,145,338 B2Granted
Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorsGeonu Kim, Yong Soon Park, Won Sun Park
Life of this patent
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Abstract
A semiconductor memory device includes a storage, a buffer, and a control logic. The storage stores a first algorithm data. The buffer stores a second algorithm data that is at least partially different from the first algorithm data. The control logic is configured to selectively receive the first algorithm data and the second algorithm data.
Claims17
A semiconductor memory device comprising:
- a storage configured to store a first algorithm data;
- a buffer configured to store a second algorithm data that is at least partially different from the first algorithm data;
- and
- a control logic configured to selectively receive the first algorithm data and the second algorithm data, the control logic including:
- a controller configured to output an address data that indicates a position in which the first or second algorithm data to be executed is stored;
- a demultiplexer configured to selectively transfer the address data to one of the storage and the buffer based on the controller;
- and
- a multiplexer configured to selectively transfer one of the first algorithm data and the second algorithm data to the controller based on the controller.
5 more elements
A semiconductor memory device comprising:
- a storage configured to store a first algorithm data;
- a memory cell array including a plurality of memory cells;
- a read and write circuit configured to perform any one of a program operation, a read operation, and an erase operation on the memory cell array;
- a buffer configured to store at least one of data that is input to the read and write circuit and data that is output from the read and write circuit, the buffer storing a second algorithm data that is at least partially different from the first algorithm data;
- and
- a control logic configured to control an operation of the read and write circuit and the buffer, the control logic including:
- a controller configured to output an address data that indicates a position in which the first or second algorithm data to be executed is stored;
- a demultiplexer configured to selectively transfer the address data to one of the storage and the buffer based on the controller;
- and
- a multiplexer configured to selectively transfer one of the first algorithm data and the second algorithm data to the controller based on the controller,
- wherein the control logic is configured to selectively receive the first algorithm data and the second algorithm data.
8 more elements
A method of operating a semiconductor memory device including a storage storing a first algorithm data, a buffer, and a control logic, the method comprising:
- inputting a second algorithm data that is at least partially different from the first algorithm data to the buffer;
- and
- selectively loading one of the first algorithm data and the second algorithm data to the control logic, and performing an operation based on the loaded algorithm data,
- wherein selectively loading one of the first algorithm data and the second algorithm data to the control logic, and performing the operation based on the loaded algorithm data comprises:
- determining whether an algorithm data to be executed is stored in the storage or in the buffer;
- outputting an address data from the control logic based on a result of the determination;
- loading the algorithm data to be executed, based on the output address data, to the control logic;
- and
- performing an operation corresponding to the loaded algorithm data.
6 more elements
Dependencies are inferred from the claim text.