Neural network accelerator run-time reconfigurability

An integrated circuit comprising:

• an accumulation memory;
• a plurality of convolution modules configured to perform mathematical operations on input values and to output values;
• a plurality of adder modules configured to sum values output from the plurality of convolution modules and to output sums to the accumulation memory;
• a plurality of convolution output interconnects connecting the plurality of convolution modules, the plurality of adder modules, and the accumulation memory, such that each convolution module has a direct connection to output values to each adder module and the accumulation memory, and each adder module has a direct connection to output sums to the accumulation memory;
• and
• a convolution output interconnect control module configured to open and close convolution output interconnects according to a convolution output connection scheme whereby each convolution module has no more than one open direct connection through the plurality of convolution output interconnects to output values to the accumulation memory or one of the plurality of adder modules.