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US 11,144,815 B2Granted
System and architecture of neural network accelerator
AssigneeOptimum Semiconductor Technologies Inc.
InventorsMayan Moudgill, John Glossner
Life of this patent
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Abstract
A system includes a memory, a processor, and an accelerator circuit. The accelerator circuit includes an internal memory, an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block to concurrently perform tasks of a neural network application assigned to the accelerator circuit by the processor.
Claims38
An accelerator circuit, comprising:
- an internal memory to store data received from a memory associated with a processor;
- an input circuit block comprising an input processor to perform a first task comprising first instructions specified according to a first instruction architecture (ISA);
- a filter circuit block comprising a filter processor to perform a second task comprising second instructions specified according to a second ISA;
- a post-processing circuit block comprising a post-processing processor to perform a third task comprising third instructions specified according to a third ISA;
- and
- an output circuit block comprising an output processor to perform a fourth task comprising fourth instructions specified according to a fourth ISA,
- wherein the input circuit block, the filter circuit block, the post-processing circuit block, and the output circuit block form an execution pipeline, and wherein at least two of the input processor, the filter processor, the post-filter processor, or the output processor perform their corresponding tasks concurrently.
4 more elements
A system, comprising:
- a memory;
- a processor to execute a neural network application comprising a first task for inputting data, a second task for filtering the data, a third task for post-processing the data, and a fourth task for outputting the data;
- and
- an accelerator circuit, communicatively coupled to the memory and the processor, the accelerator circuit comprising:
- an internal memory to store data received from the memory;
- an input circuit block comprising an input processor to perform the first task comprising first instructions specified according to a first instruction architecture (ISA);
- a filter circuit block comprising a filter processor to perform the second task comprising second instructions specified according to a second ISA;
- a post-processing circuit block comprising a post-processing processor to perform the third task comprising third instructions specified according to a third ISA;
- and
- an output circuit block comprising an output processor to perform the fourth task comprising fourth instructions specified according to a fourth ISA,
- wherein at least two of the input processor, the filter processor, the post-filter processor, or the output processor perform their corresponding tasks concurrently, and wherein each of the input processor, the filter processor, the post-processing processor, or the output processor is a reduced instruction set computer (RISC) processor designed with a common ISA and further enhanced with a respective unique set of instructions.
8 more elements
Dependencies are inferred from the claim text.