Fingerprint sensor and terminal device

A terminal device, wherein the terminal device comprises a fingerprint sensor;

• the fingerprint sensor comprises a plurality of integration circuits and a negative feedback circuit;
• wherein the negative feedback circuit is connected to the plurality of integration circuits for respectively fixing an input common mode voltage of each of the integration circuits as a reset bias voltage when the plurality of integration circuits are in a reset phase;
• and
• each of the integration circuits comprises an input terminal, a feedback terminal, and an output terminal, and each of the integration circuits comprises an integration capacitor and corresponds to a fingerprint capacitor respectively, wherein the integration capacitor is connected between the input terminal and the output terminal, and the feedback terminal and the output terminal are connected to the negative feedback circuit to form a negative feedback loop, and each of the integration circuits is configured to perform integration processing by transferring a charge of the corresponding fingerprint capacitor to the integration capacitor when in an integration phase respectively, and output an output voltage related to the corresponding fingerprint capacitor;
• wherein the negative feedback circuit comprises an operational amplifier, and the operational amplifier is configured to form a negative feedback loop with the integration circuit when the integration circuit is in the reset phase;
• wherein the negative feedback circuit comprises an offset correction circuit, and the reset phase of the integration circuit includes a first phase and a second phase, wherein the offset correction circuit is configured to acquire an offset voltage at two input terminals of the operational amplifier when the integration circuit is in the first phase, and the offset voltage is used to perform offset correction on the integration circuit in the second phase, so that the input common mode voltage of the integration circuit is fixed as the reset bias voltage, wherein the offset correction circuit comprises a zeroing capacitor;
• wherein one terminal of the zeroing capacitor is connected to a non-inverting input terminal of the operational amplifier, and also connected to an output terminal of the integration circuit when the integration circuit is in the first phase, while disconnected from the output terminal of the integration circuit when the integration circuit is in the second phase;
• and the other terminal of the zeroing capacitor is connected to an inverting input terminal of the operational amplifier when the integration circuit is in the first phase, while connected to the output terminal of the integration circuit, and disconnected from the inverting input terminal of the operational amplifier when the integration circuit is in the second phase.