Layout checking system and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYao-Jen Hsieh, Kai-Ming Liu
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYao-Jen Hsieh, Kai-Ming Liu
Estimating the term…
A method includes operation below: extracting layout patterns that include interconnection layers between a first terminal and a second terminal coupled to the first terminal, in a layout design of a circuit; comparing a first portion of the layout patterns with a first coding portion that specifies a first layout constraint, in which the first portion of the layout patterns is extracted in a sequence starting from the first terminal or to the first terminal; comparing a second portion of the layout patterns with a second coding portion that specifies a second layout constraint, in which the second portion of the layout patterns is extracted in a sequence from the second terminal or to the second terminal; in response to comparisons, initiating fabrication of at least one element of the circuit according to the layout design.
A method, comprising:
A system, comprising:
A non-transitory computer readable medium comprising instructions that when executed perform a method, the method comprising:
Dependencies are inferred from the claim text.