Loading patent…
AssigneeInternational Business Machines Corporation
InventorNitin Srimal
Estimating the term…
A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
A method comprising:
A system comprising:
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computing device to cause the computing device to:
Dependencies are inferred from the claim text.