Extensible layer mapping for in-design verification

An apparatus, comprising:

• a processor;
• and
• a non-transitory computer-readable medium comprising stored instructions, which when executed by the processor, cause the processor to:
• convert a first integrated circuit (IC) design layout having in-design layers into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the first IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers, wherein each layer derivation rule includes a condition that must be satisfied by parameters of a given shape in the first IC design layout for the layer derivation rule to apply to the given shape, and wherein the condition includes one or more of:
• a first term that checks if the given shape is in an active or a non-active region, a second term that checks if the given shape is in an n-type or a p-type region, and a third term that checks if the given shape is covered by a recognition layer corresponding to a type of module;
• generate a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool;
• and
• perform parasitic extraction on the first IC design layout by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

A method for in-design parasitic extraction, the method comprising:

• converting, by using a computer, a first integrated circuit (IC) design layout having in-design layers into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the first IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers, wherein each layer derivation rule includes a condition that must be satisfied by parameters of a given shape in the first IC design layout for the layer derivation rule to apply to the given shape, and wherein the condition includes one or more of:
• a first term that checks if the given shape is in an active or a non-active region, a second term that checks if the given shape is in an n-type or a p-type region, and a third term that checks if the given shape is covered by a recognition layer corresponding to a type of module;
• generating a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool;
• and
• performing parasitic extraction on the first IC design layout by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.