System with secure SoC connections among IP and multiple GPIOs, and corresponding method

A system, comprising:

• an integrated circuit, including:
• one or more intellectual property (IP) cores;
• one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports;
• and
• one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface, wherein a security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface;
• and
• a peripheral device coupled to a port of the GPIO interface, wherein the security circuit, in operation:
• enables communication between the IP core and the GPIO interface coupled to the security circuit when the indication of the security status of the IP core indicates the IP core is secure and the indication of the security status of the GPIO interface indicates the GPIO interface is secure;
• enables communication between the IP core and the GPIO interface coupled to the security circuit when the indication of the security status of the IP core indicates the IP core is not secure and the indication of the security status of the GPIO interface indicates the GPIO interface is not secure;
• disables communication between the IP core and the GPIO interface coupled to the security circuit when the indication of the security status of the IP core indicates the IP core is secure and the indication of the security status of the GPIO interface indicates the GPIO interface is not secure;
• and
• disables communication between the IP core and the GPIO interface coupled to the security circuit when the indication of the security status of the IP core indicates the IP core is not secure and the indication of the security status of the GPIO interface indicates the GPIO interface is secure, wherein a memory of a security control circuit stores indications of the security statuses of the one or more IP cores and memories of GPIO control circuits of the GPIO interfaces store indications of the security statuses of the one or more GPIO interfaces.

A method, comprising:

• retrieving, by a security circuit of an integrated circuit coupled between an intellectual property (IP) core of the integrated circuit and a General Purpose Input/Output (GPIO) interface of the integrated circuit, an indication of the security status of the IP core from a memory of a security control circuit;
• retrieving, by the security circuit, an indication of the security status of the GPIO interface from a control circuit of the GPIO interface;
• and
• selectively enabling, by the security circuit, communications between the IP core and the GPIO interface based on the received indication of the security status of the IP core, the received indication of the security status of the GPIO interface or both the received indication of the security status of the IP core and the received indication of the security status of the GPIO interface, wherein the method comprises:
• enabling communication between the IP core and the GPIO interface when the indication of the security status of the IP core indicates the IP core is secure and the indication of the security status of the GPIO interface indicates the GPIO interface is secure;
• enabling communication between the IP core and the GPIO interface when the indication of the security status of the IP core indicates the IP core is not secure and the indication of the security status of the GPIO interface indicates the GPIO interface is not secure;
• disabling communication between the IP core and the GPIO interface when the indication of the security status of the IP core indicates the IP core is secure and the indication of the security status of the GPIO interface indicates the GPIO interface is not secure;
• and
• disabling communication between the IP core and the GPIO interface when the indication of the security status of the IP core indicates the IP core is not secure and the indication of the security status of the GPIO interface indicates the GPIO interface is secure.