Method and apparatus for digital only secure test mode entry

A test control method comprising:

• performing, by a test control device, an admissions control process to authorize test mode access to a secure circuit in an integrated circuit device;
• generating an authentication control pattern in response to authorizing test mode access to the secure circuit in the integrated circuit device;
• storing the authentication control pattern in a digital non-resettable state retention storage circuit at the test control device;
• and
• generating, by the test control device, a test mode enable signal with combinatorial logic circuitry which detects when the digital non-resettable state retention storage circuit stores the authentication control pattern.

A fully digital test control access system for an integrated circuit, comprising:

• a secure unit comprising one or more logic elements that are protected from test access during normal operation;
• test circuitry connected to the one or more logic elements, wherein the test circuitry is configured to provide test access to the one or more logic elements in response to a test mode enable signal;
• and
• test control access circuitry connected to authorize and enable test access by the test circuitry to the secure unit, the test control access circuitry comprising:
• a digital non-resettable state retention storage circuit for storing an authentication control pattern which is generated in response to authorized test mode access to the secure unit;
• and
• combinatorial logic circuitry for generating the test mode enable signal when the digital non-resettable state retention storage circuit stores the authentication control pattern.