Optimal I3C in-band interrupt handling through reduced slave arbitration cycles

An apparatus configured for data communication, comprising:

• a bus interface circuit having a line driver configured to couple the apparatus to a data line of a serial bus operated in accordance with an Improved Inter-Integrated Circuit (I3C) protocol;
• and
• a processor configured to:
• assert an in-band interrupt request on the serial bus;
• transmit a slave address associated with the apparatus over the data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted;
• ignore a change in signaling state of the data line indicating transmission by a higher-priority device while transmitting the slave address during the first bus arbitration transaction;
• and
• participate in one or more transactions responsive to assertion of the in-band interrupt request and transmission of the slave address.

A method for bus arbitration performed at a master device, comprising:

• configuring two or more slave devices to ignore signaling state of a data line of a serial bus while transmitting their respective slave addresses during bus arbitration transactions;
• detecting an in-band interrupt request from the serial bus when the serial bus is operated in accordance with Improved Inter-Integrated Circuit (I3C) protocols;
• receiving a composite address generated by the two or more slave devices when the two or more slave devices are participating in a first bus arbitration transaction conducted in response to the in-band interrupt request;
• identifying the two or more slave devices from zero-value bits in the composite address;
• and
• initiating one or more transactions responsive to the in-band interrupt request.

An apparatus configured for data communication, comprising:

• a bus interface circuit having a line driver configured to couple the apparatus to a data line of a serial bus operated in accordance with Improved Inter-Integrated Circuit (I3C) protocols;
• and
• a processor configured to:
• configure two or more slave devices to ignore signaling state of the data line while transmitting their respective slave addresses during bus arbitration transactions;
• detect an in-band interrupt request from the serial bus;
• receive a composite address generated by the two or more slave devices when the two or more slave devices are participating in a first bus arbitration transaction conducted in response to the in-band interrupt request;
• identify the two or more slave devices from zero-value bits in the composite address;
• and
• initiate one or more transactions responsive to the in-band interrupt request.