Atomic instruction having a local scope limited to an intermediate cache level
AssigneeKalray
InventorsBenoit Dupont De Dinechin, Marta Rybczynska, Vincent Ray
Life of this patent
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Abstract
The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.
Claims10
A processor comprising:
- multiple similar cores divided into multiple groups;
- distinct cache memories respectively assigned to the groups, each distinct cache memory being shared by the cores of the respective group;
- in an instruction set of the processor, an atomic read-modify-write instruction that takes as a parameter a memory address of a shared variable, and has a local scope limited to a group of cores including a core that executes the atomic instruction;
- and
- a cache memory controller configured to:
- process each local scope atomic instruction executed by a core of a given group by locally locking in the distinct cache memory of the given group a cache line allocated to the address of the shared variable, while simultaneously authorizing read and write access to the shared variable to cores outside the given group during execution of the local scope atomic instruction.
A method for updating a variable shared between multiple similar processor cores, the method comprising:
- distributing the cores in multiple groups assigned to respective distinct cache memories;
- executing in a core of a given group an atomic read-modify-write instruction having a local scope limited to the given group, with a memory address of the shared variable as a parameter;
- performing operations of the atomic instruction in the distinct cache memory of the given group, a cache line allocated to the memory address;
- and
- locking the cache line locally to the given group while simultaneously authorizing read and write access to the shared variable by cores outside the given group during execution of the local scope atomic instruction.
Dependencies are inferred from the claim text.