System for address mapping and translation protection

An address translation method, comprising:

• determining, by processor circuitry, whether a first received linear address included in a first received command is included in a processor protected linear range (PLR);
• responsive to a first determination that the first received linear address included in the first received command falls outside the processor protected linear range:
• converting, by the processor circuitry, the first received linear address to a first hardware physical address (HPA) using a first page table;
• and
• providing, by the processor circuitry, a first guest linear address mapping to the first HPA to translation lookaside buffer (TLB) circuitry communicatively coupled to the processor circuitry;
• responsive to a second determination that a second received linear address included in a second received command falls inside the processor protected linear range:
• converting, by the processor circuitry, the second received linear address to a second HPA using a second page table;
• and
• providing, by the processor circuitry, a second guest linear address mapping to the second HPA to the TLB circuitry.

A non-transitory storage device that includes machine-readable instructions that, when executed by processor circuitry, cause the processor circuitry to:

• determine whether a first received linear address included in a first received command is included in a processor protected linear range (PLR);
• responsive to a first determination that the first received linear address included in the first received command falls outside the processor protected linear range:
• convert the first received linear address to a first hardware physical address (HPA) using a first page table;
• and
• provide a first guest linear address mapping to the first HPA to translation lookaside buffer (TLB) circuitry communicatively coupled to the processor circuitry;
• responsive to a second determination that a second received linear address included in a second received command falls inside the processor protected linear range:
• convert the second received linear address to a second HPA using a second page table;
• and provide a second guest linear address mapping to the second HPA to the TLB circuitry.