US 11,144,472 B2Granted

Memory management apparatus and method for managing different page tables for different privilege levels

AssigneeIntel Corporation

InventorsScott Dion Rodgers, Robert S. Chappell, Barry E. Huntley

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Abstract

An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

Claims29

Dependent claims

A processor comprising:

a first control register to store a first base address associated with program code executed at a first privilege level;
a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level;
a third control register to store a context identifier to identify a context for at least a portion of the program code executed at the second privilege level, wherein the context identifier to identify the context for the at least portion of the program code executed at the second privilege level is changeable at the first privilege level but not the second privilege level, wherein another context identifier to identify a context for at least the portion of the program code executed at the first privilege level, and wherein the another context identifier is unchangeable at the first privilege level and the second privilege level;
and
address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

2 more elements

A method comprising:

storing a first base address associated with program code executed at a first privilege level in a first control register;
storing a second base address associated with program code executed at a second privilege level in a second control register, the second privilege level lower than the first privilege level;
storing a context identifier in a third control register to identify a context for at least a portion of the program code executed at the second privilege level, wherein the context identifier to identify the context for the at least portion of the program code executed at the second privilege level is changeable at the first privilege level but not the second privilege level, wherein another context identifier to identify a context for at least the portion of the program code executed at the first privilege level, and wherein the another context identifier is unchangeable at the first privilege level and the second privilege level;
receiving a first address translation request originating from the program code executed at the first privilege level;
identifying a first base translation table using the first base address responsive to the first address translation request;
receiving a second address translation request originating from the program code executed at the second privilege level;
and
identifying a second base translation table using the second base address responsive to the second address translation request.

5 more elements

A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform:

storing a first base address associated with program code executed at a first privilege level in a first control register;
storing a second base address associated with program code executed at a second privilege level in a second control register, the second privilege level lower than the first privilege level;
storing a context identifier in a third control register to identify a context for at least a portion of the program code executed at the second privilege level, wherein the context identifier to identify the context for the at least portion of the program code executed at the second privilege level is changeable at the first privilege level but not the second privilege level, wherein another context identifier to identify a context for at least the portion of the program code executed at the first privilege level, and wherein the another context identifier is unchangeable at the first privilege level and the second privilege level;
receiving a first address translation request originating from the program code executed at the first privilege level;
identifying a first base translation table using the first base address responsive to the first address translation request;
receiving a second address translation request originating from the program code executed at the second privilege level;
and
identifying a second base translation table using the second base address responsive to the second address translation request.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/367,103Filed 27 Mar 2019
Published: US 2020/0310978 A11 Oct 2020
Granted: 12 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 12/1009
Address translation: using page tables, e.g. page table structures
G06F 12/109
Address translation: for multiple virtual address spaces, e.g. segmentation
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1036
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: for multiple virtual address spaces,…