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US 11,144,466 B2Granted
Memory device with local cache array
AssigneeIntel Corporation
InventorsJongwon Lee, Vivek Kozhikkottu, Kuljit S. Bains, Hussein Alameer
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Abstract
An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.
Claims20
A memory apparatus, comprising:
- a memory cell array logically organized in two or more banks of at least two rows and two columns per bank;
- two or more local caches respectively coupled to the two or more banks of the memory cell array, wherein each local cache has a size which is an integer multiple of a memory page size of the memory cell array;
- and
- logic to decode local cache specific commands from a memory controller to manage direct access to the two or more local caches.
1 more element
A memory system, comprising:
- a memory controller;
- and
- a memory device communicatively coupled to the memory controller, the memory device including:
- a memory cell array logically organized in two or more banks of at least two rows and two columns per bank,
- two or more row caches respectively coupled to the two or more banks of the memory cell array, wherein each row cache has a size which is an integer multiple of a memory page size of the memory cell array, and
- logic to decode row cache specific commands from the memory controller to manage direct access to the two or more row caches.
3 more elements
A method of controlling memory, comprising:
- logically organizing a memory cell array in two or more banks of at least two rows and two columns per bank;
- providing two or more local caches respectively coupled to the two or more banks of the memory cell array, wherein each local cache has a size which is an integer multiple of a memory page size of the memory cell array;
- and
- decoding local cache specific commands from a memory controller to manage direct access to the two or more local caches.
1 more element
Dependencies are inferred from the claim text.