Data access method and apparatus

An interface card comprising:

• a receiver configured to receive a first data write instruction and a first data read instruction from a host;
• and
• a processor coupled to the receiver and configured to:
• obtain data and a destination address of the data, wherein the first data read instruction comprises the destination address, and wherein the destination address is an address at which the data is to be written into a storage subsystem of a storage device;
• write the data and the destination address into a cache of the storage device without consuming any resources of a second processor on the storage device;
• generate a second data write instruction, wherein the second data write instruction comprises a source address and the destination address, wherein the source address is an address at which the data is stored in the cache, and wherein the second data write instruction instructs the storage subsystem to read the data from the cache according to the source address and to write the data into storage space corresponding to the destination address;
• send the second data write instruction from a cache controller of the storage device to the storage subsystem without consuming any resources of the second processor;
• generate a second data read instruction;
• and
• write the second data read instruction into the cache, wherein the second data read instruction comprises the destination address and a cache address at which the data is to be written into the cache from the storage subsystem.

A storage device comprising:

• a cache;
• an interface card coupled to the cache and configured to:
• receive a first data write instruction from a host;
• obtain data and a destination address of the data, wherein the destination address indicates an address at which the data is to be written;
• write the data and the destination address into the cache without consuming any resources of a processor on the storage device;
• generate a second data write instruction, wherein the second data write instruction comprises a source address and the destination address, and wherein the source address is an address at which the data is stored in the cache;
• receive a first data read instruction from the host, wherein the first data read instruction comprises the destination address;
• generate a second data read instruction;
• and
• write the second data read instruction into the cache, wherein the second data read instruction comprises the destination address and a cache address at which the data is to be written into the cache from the storage subsystem;
• a cache controller coupled to the interface card and the cache and configured to send the second data write instruction without consuming any resources of the processor;
• and
• a storage subsystem coupled to the cache controller and configured to:
• receive the second data write instruction from the cache controller;
• read the data from the cache according to the source address;
• and
• write the data into storage space corresponding to the destination address.