Information processing device, access controller, information processing method, and computer program for issuing access requests from a processor to a sub-processor
AssigneeSony Interactive Entertainment Inc.
InventorHideyuki Saito
Life of this patent
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Abstract
Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.
Claims8
An information processing apparatus comprising:
- a main processor configured to issue an access request to access a file stored in a secondary storage,
- wherein the access request is received at the main processor from an application program;
- a sub-processor directly coupled with the main processor via a bus configured to:
- receive the access request,
- divide the access request into a plurality of secondary access requests;
- issue the secondary access requests to access data blocks formed by dividing the file;
- and
- notify the main processor of a point in time at which all the data blocks are read out and made accessible;
- and
- a controller configured to:
- accept the secondary access requests from the sub-processor;
- read the data blocks individually by parallelly processing the secondary access requests using a plurality of channels disposed in the secondary storage;
- and
- notify the sub-processor a timing of when each of the data blocks is read out,
- wherein the sub-processor has lower computational capability that the main processor.
A non-transitory computer readable medium having stored thereon a program executed by a processor, the program comprising:
- a primary access request issuing section causing a main processor to issue an access request,
- wherein the access request is received at the main processor from an application program;
- an access request dividing section configured to:
- accept, at a sub-processor directly coupled to the main processor via a bus, an access request to access a file stored in a secondary storage of an information processing apparatus;
- and
- divide the accepted access request into a plurality of secondary access requests to access data blocks formed by dividing the file;
- a secondary access request issuing section configured to issue the secondary access requests to a controller that parallelly processes the secondary access requests using a plurality of channels disposed in the secondary storage;
- and
- a notifying section configured to acquire a notification from the controller every time one of the data blocks is read out, the notifying section further notifying the another processor of a point in time at which all the data blocks are read out and made accessible,
- wherein the sub-processor has lower computation capability that the main processor.
An information processing method comprising the steps of:
- causing a main processor to issue an access request to access a file stored in a secondary storage,
- wherein the access request is received at the main processor from an application program;
- causing a sub-processor directly coupled to the main processor via a bus to accept the access request, divide the access request into a plurality of secondary access requests, and issue the secondary access requests to access data blocks formed by dividing the file;
- causing a controller to accept the secondary access requests from the sub-processor, read the data blocks individually by parallelly processing the secondary access requests using a plurality of channels disposed in the secondary storage, and notify the sub-processor of when one of the data blocks is read out;
- and
- causing the sub-processor to notify the main processor of a point in time at which all the data blocks are read out and made accessible,
- wherein the sub-processor has lower computation capability that the main processor.
Dependencies are inferred from the claim text.