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US 11,144,459 B2Granted
Cache coherency adopted GPU shared memory
AssigneeInternational Business Machines Corporation
InventorsZhichao Li, Li Li, Riaz Y. Hussain, Ben Gibbs, Su Liu
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Abstract
An approach is provided in which a system includes a GPU cluster. The GPU cluster includes multiple GPU nodes, that each includes a GPU core and a corresponding local cache. The GPU cluster also includes a shared memory and an internal bus that maintains cache coherency between the shared memory and the local caches included in the GPU nodes.
Claims17
A system comprising:
- a first processing layer comprising:
- a host central processing unit (CPU);
- a point to point (P2P) high speed bus coupled to the host CPU;
- and
- a graphics processing unit (GPU) cluster comprising a second processing layer, wherein the second processing layer further comprises:
- a plurality of GPU nodes, each of the plurality of GPU nodes consisting of a GPU core, a local I/O, and a local cache dedicated to the GPU core;
- a shared memory accessible by each of the plurality of GPU nodes;
- an internal bus that connects the shared memory in the GPU cluster to each of the local I/Os in the plurality of GPU nodes and maintains cache coherency between the shared memory and each of the local caches in each of the plurality of GPU nodes using a cache coherency protocol;
- and
- an input/output interface that connects the GPU cluster to the P2P high speed bus and also connects to the internal bus in the GPU cluster.
7 more elements
The system of 2 wherein the one or more different P2P high speed buses maintain cache coherency between the shared memory in the GPU cluster and a different shared memory in a different one of the plurality of GPU clusters.
A method implemented by an information handling system, the method comprising:
- sending a set of data from a host processor over a point to point (P2P) high speed bus to a graphics processing unit (GPU) cluster, wherein the information handling system comprises a first processing layer including the host processor, the P2P high speed bus, and the GPU cluster, and wherein the GPU cluster comprises a second processing layer including a plurality of GPU nodes, a shared memory accessible by each of the plurality of GPU nodes, an internal bus, and an input/output interface;
- storing the set of data in a first local cache by a first GPU core, wherein the first GPU core and the first local cache are included in a third processing layer of a first one of the plurality of GPU nodes consisting of the first GPU core, the first local cache, and a first local I/O;
- utilizing a cache coherency protocol to copy the set of data over the internal bus from the first local cache to the shared memory;
- utilizing the cache coherency protocol to copy the set of data from the shared memory to a second one of the plurality of GPU nodes consisting of a second GPU core, a second local cache, and a second local I/O, wherein the second GPU node stores the set of data in the second local cache;
- accessing, by a second GPU core included in the second GPU node, the set of data from the second local cache;
- sending a different set of data over the point to point (P2P) high speed bus from the host CPU to an I/O interface in the GPU cluster, wherein the I/O interface transfers the different set of data to the shared memory over the internal bus;
- utilizing the cache coherency protocol to copy the different set of data from the shared memory to the first local cache;
- and
- accessing the different set of data from the first local cache by the first GPU core.
6 more elements
An information handling system comprising:
- one or more processors;
- a memory coupled to at least one of the processors;
- a set of computer program instructions stored in the memory and executed by at least one of the processors in order to perform actions of:
- sending a set of data from a host processor over a point to point (P2P) high speed bus to a graphics processing unit (GPU) cluster, wherein the information handling system comprises a first processing layer including the host processor, the P2P high speed bus, and the GPU cluster, and wherein the GPU cluster comprises a second processing layer including a plurality of GPU nodes, a shared memory accessible by each of the plurality of GPU nodes, an internal bus, and an input/output interface;
- storing the set of data in a first local cache by a first GPU core, wherein the first GPU core and the first local cache are included in a third processing layer of a first one of the plurality of GPU nodes consisting of the first GPU core, the first local cache, and a first local I/O;
- utilizing a cache coherency protocol to copy the set of data over the internal bus from the first local cache to the shared memory;
- utilizing the cache coherency protocol to copy the set of data from the shared memory to a second one of the plurality of GPU nodes consisting of a second GPU core, a second local cache, and a second local I/O, wherein the second GPU node stores the set of data in the second local cache;
- accessing, by a second GPU core included in the second GPU node, the set of data from the second local cache;
- sending a different set of data over the point to point (P2P) high speed bus from the host CPU to an I/O interface in the GPU cluster, wherein the I/O interface transfers the different set of data to the shared memory over the internal bus;
- utilizing the cache coherency protocol to copy the different set of data from the shared memory to the first local cache;
- and
- accessing the different set of data from the first local cache by the first GPU core.
9 more elements
Dependencies are inferred from the claim text.