Hardware coherence signaling protocol

A method, comprising:

• receiving, by a level two (L2) controller, a read request from a level one (L1) controller as a single transaction;
• wherein the read request comprises:
• a read address;
• a first indication of an address and a coherence state of a cache line A to be moved from a L1 main cache to a L1 victim cache to allocate space for data returned in response to the read request;
• and
• a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

A level two (L2) cache subsystem, comprising:

• a L2 main cache;
• a shadow L1 main cache;
• a shadow L1 victim cache;
• and
• a L2 controller configured to receive a read request in a single transaction from a level one (L1) controller, the read request comprising:
• a read address;
• a first indication of an address and a coherence state of a cache line A to be moved from a L1 main cache to a L1 victim cache to allocate space for data returned in response to the read request;
• and
• a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.