Apparatus, systems, and methods to detect and/or correct bit errors using an in band link over a serial peripheral interface

A memory controller to detect and report a bit error in a memory device over an in band link, comprising:

• a port coupleable to the in band link, wherein the in band link includes one or more serial peripheral interface (SPI) bus lines;
• and
• a logic unit coupled to the port to:
• in response to an in band request to write and/or erase data, calculate or determine an error correction code (ECC) and store parity data in the memory device coupled to a processor;
• and
• after receiving a subsequent request to read the data, access the stored parity data to check the ECC for a bit error in the data and if a bit error is detected, report to a serial bus controller of a master or host device the detected bit error on an in band error interrupt signal over the one or more SPI bus lines, wherein as part of an optional correction of the bit error by the serial bus controller, if the bit error is to be corrected, the logic unit receives from the serial bus controller, a command to reprogram contents of an address in the memory device, or if the bit error is to remain uncorrected, the logic unit receives from the serial bus controller a band reset command to abort read or write functions.