Memory controller storing data in approximate memory device based on priority-based ECC, non-transitory computer-readable medium storing program code, and electronic device comprising approximate memory device and memory controller

A non-transitory computer-readable medium storing a program code that, when executed by a processor, causes the processor to:

• replace some bits of first data with parity bits, the parity bits associated with an error correction operation;
• generate second data including remaining bits of the first data and the parity bits replaced from the some bits;
• and
• generate a write command for storing the second data in a memory device, wherein
• a memory cell array of the memory device is divided into a first zone and a second zone,
• the second data are stored in the second zone, and
• the program code, when executed by the processor, further causes the processor to receive a bit error rate (BER) and adjust a refresh rate of the first zone and a refresh rate of the second zone based on the received BER.

An electronic device comprising:

• a processor configured to generate first data;
• a memory controller configured to replace some bits of the first data with parity bits and to generate second data including remaining bits of the first data and the parity bits replaced from the some bits, the parity bits associated with an error correction operation;
• and
• a memory device configured to store the second data transmitted from the memory controller, wherein
• a memory cell array of the memory device is divided into a first zone and a second zone,
• the second data are stored in the second zone, and
• the memory controller is further configured to receive a bit error rate (BER) and adjust a refresh rate of the first zone and a refresh rate of the second zone based on the received BER.