US 11,144,323 B2Granted

Independent mapping of threads

AssigneeInternational Business Machines Corporation

InventorsSam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto

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Abstract

Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.

Claims18

Dependent claims

A method comprising:

receiving, from a dispatch queue, a first number of threads;
allocating, by a network, the received first number of threads to a first even plurality of parallel execution slices;
executing the first number of threads on the first even plurality of parallel execution slices;
writing results of the execution of the first number of threads to a set of register files associated with the first even plurality of parallel execution slices;
receiving, from the dispatch queue, a second number of threads;
allocating, by the network, the received second number of threads to a second even plurality of parallel execution slices;
determining the first number of threads is less than the second number of threads;
and
creating a new set of register files associated with the second even plurality of execution slices, for the second number of threads;
executing the second number of threads on the second even plurality of execution slices;
and
writing results of the execution of the second number of threads to a set of register files associated with the second even plurality of parallel execution slices.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/676,763Filed 7 Nov 2019 · continuation
Priority: 30 Sep 2014
Published: US 2020/0073668 A15 Mar 2020
Granted: 12 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3012
Register arrangements: organisation of register space, e.g. banked or distributed register file
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/3891
Controlled by multiple instructions, e.g. MIMD, decoupled access or execute: organised in groups of units sharing resources, e.g. clusters

Family

Application14/501,152Parent of this continuation · filed 30 Sep 2014
Application14/869,305Parent of this continuation · filed 29 Sep 2015
US 9,720,696 B2Parent of this continuation · filed 1 Aug 2017
Application15/805,267Parent of this continuation · filed 7 Nov 2017
US 9,870,229 B2Parent of this continuation · filed 16 Jan 2018
US 2020/0073668 A1Pre-grant publication · published 5 Mar 2020
US 10,545,762 B2Parent of this continuation
US 2016/0092231 A1Published application
US 2016/0092276 A1Published application
US 2018/0067746 A1Published application
US 11,144,323 B2This patent

From the US filing history. Foreign family members aren’t listed.