US 11,144,322 B2Granted

Code and data sharing among multiple independent processors

AssigneeMediatek Inc.

InventorsHsiao Tzu Feng, Chia-Wei Chang, Li-San Yao

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Abstract

A system includes a memory and multiple processors. The memory further includes a shared section and a non-shared section. The processors further include at least a first processor and a second processor, both of which read-only access to the shared section of the memory. The first processor and the second processor are operable to execute shared code stored in the shared section of the memory, and execute non-shared code stored in a first sub-section and a second sub-section of the non-shared section, respectively. The first processor and the second processor execute the share code according to a first scheduler and a second scheduler, respectively. The first scheduler operates independently of the second scheduler.

Claims18

Dependent claims

A system operative to share code, comprising:

a memory including a shared section and a non-shared section;
and
a plurality of processors including at least a first processor and a second processor, the first processor and the second processor having read-only access to the shared section of the memory, wherein the first processor and the second processor are operable to:
execute shared code stored in the shared section of the memory according to a first scheduler and a second scheduler, respectively, wherein the first scheduler operates independently of the second scheduler,
execute non-shared code stored in a first sub-section and a second sub-section of the non-shared section, respectively, and
execute a read or write instruction having an operand at a first address in the first sub-section according to the shared code, and
wherein, to access the operand, the second processor at runtime is further operable to map the first address to a second address in the second sub-section according to an address mapping method.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/675,212Filed 5 Nov 2019
Published: US 2021/0132952 A16 May 2021
Granted: 12 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/544
Interprogram communication: buffers; Shared memory; Pipes
A61F 5/0102
Orthopaedic devices, e.g. long-term immobilising or pressure directing devices for treating broken or deformed bones such as splints, casts or…
A61F 5/0193
Orthopaedic devices, e.g. long-term immobilising or pressure directing devices for treating broken or deformed bones such as splints, casts or…