Store hit multiple load side register for preventing a subsequent store memory violation

A computer-implemented method, comprising:

• based on detecting a first store hit multiple load condition in a processor, updating a store hit multiple load side register (SHMLSR) of the processor to hold information corresponding to a first store instruction that triggered the detected first store hit multiple load condition, wherein updating the SHMLSR of the processor comprises:
• setting a valid indicator in the SHMLSR;
• and
• updating a data field of the SHMLSR to hold an instruction identifier corresponding to the first store instruction;
• based on detecting a second store hit multiple load condition in the processor, determining that the valid indicator in the SHMLSR is set;
• based on determining that the valid indicator is set, not updating the SHMLSR based on the second store hit multiple load condition in the processor;
• based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the SHMLSR;
• based on determining that the second store instruction corresponds to the information in the SHMLSR, tagging the second store instruction with an operand store compare mark;
• and
• upon completion of the second store instruction, unsetting the valid indicator in the SHMLSR.

An apparatus, comprising program code executable by a processor to:

• based on detecting a first store hit multiple load condition in the processor, update a store hit multiple load side register (SHMLSR) of the processor to hold information corresponding to a first store instruction that triggered the detected first store hit multiple load condition, wherein updating the SHMLSR of the processor comprises:
• setting a valid indicator in the SHMLSR;
• and
• updating a data field of the SHMLSR to hold an instruction identifier corresponding to the first store instruction;
• based on detecting a second store hit multiple load condition in the processor, determine that the valid indicator in the SHMLSR is set;
• based on determining that the valid indicator is set, not update the SHMLSR based on the second store hit multiple load condition in the processor;
• based on issuing a second store instruction in the processor, determine whether the second store instruction corresponds to the information in the SHMLSR;
• based on determining that the second store instruction corresponds to the information in the SHMLSR, tag the second store instruction with an operand store compare mark;
• and
• upon completion of the second store instruction, unset the valid indicator in the SHMLSR.