Generating synchronous digital circuits from source code constructs that map to circuit implementations

A computing system comprising:

• one or more processing units;
• and
• a computer-readable storage medium having computer-executable instructions stored thereupon which, when executed by the one or more processing units, cause the computing system to:
• store source code expressed in a multi-threaded imperative programming language, the source code comprising a construct that maps to a circuit implementation, the construct comprising a condition statement, and wherein the circuit implementation comprises:
• a first hardware pipeline implementing first functionality defined by first instructions located prior to the condition statement in the source code, the first hardware pipeline having an output connected to a queue, and
• a second hardware pipeline implementing second functionality defined by second instructions located after the condition statement in the source code and based on the output of the first hardware pipeline, the second hardware pipeline having an input connected to the queue connected to the output of the first hardware pipeline, and wherein the second hardware pipeline processes a value received from the first hardware pipeline by the queue only when the condition statement is evaluated as true;
• compile the construct to output a circuit description in a hardware description language (HDL);
• and
• generate, based on the circuit description, a synchronous digital circuit comprising the circuit implementation.

A computer-readable storage medium having computer-executable instructions stored thereupon which, when executed by one or more processing units, cause a computing system to:

• store source code expressed in a multi-threaded imperative programming language, the source code comprising a construct that maps to a circuit implementation, the construct comprising a condition statement, and wherein the circuit implementation comprises:
• a first hardware pipeline implementing first functionality defined by first instructions located prior to the condition statement in the source code, the first hardware pipeline having an output connected to a queue, and
• a second hardware pipeline implementing second functionality defined by second instructions located after the condition statement in the source code and based on the output of the first hardware pipeline, the second hardware pipeline having an input connected to the queue connected to the output of the first hardware pipeline, and wherein the second hardware pipeline processes a value received from the first hardware pipeline by the queue only when the condition statement is evaluated as true;
• compile the construct to output a circuit description in a hardware description language (HDL);
• and
• generate, based on the circuit description, a synchronous digital circuit comprising the circuit implementation.