Write leveling a memory device
AssigneeMicron Technology, Inc.
InventorsDaniel B. Penney, Liang Chen
Life of this patent
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Abstract
A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.
Claims19
A memory device, comprising:
- a command interface configured to receive write commands from a host device;
- an input-output interface configured to receive a data strobe from the host device;
- and
- internal write circuitry configured to;
- launch an internal write signal a number of clock cycles prior to a column address strobe write latency (CWL) based at least in part on the write commands, wherein timing of the launch of the internal write signal is based at least in part on an indication from the host device that indicates the number as an indication of when to launch the internal write signal relative to the CWL for the memory device, wherein the internal write signal is launched relative to the a data strobe signal;
- and
- adjust the data strobe signal by:
- incrementally shifting the data strobe signal in a first direction until a capture failure occurs;
- and
- after the capture failure occurs, shifting the data strobe signal in a second direction by a half cycle, wherein the second direction is in an opposite direction of the first direction.
A method, comprising:
- outputting a clock;
- outputting a data strobe signal;
- synchronizing the clock and the data strobe signal at a pin of a memory device as an external write leveling operation;
- determining a number of cycles to cause the memory device to launch an internal write signal as an internal write leveling operation to cause capture of the internal write signal at a location relative to the data strobe signal, wherein the number of cycles comprises the number of cycles shorter than a column address strobe write latency (CWL) duration for the memory device;
- sending the number of cycles to the memory device;
- and
- adjusting the data strobe signal by less than a cycle as a fine adjustment, wherein the fine adjustment comprises:
- incrementally shifting the data strobe signal in a first direction until a capture failure occurs;
- and
- after the capture failure occurs, shifting the data strobe signal in a second direction by a half cycle, wherein the second direction is in an opposite direction of the first direction.
A method comprising:
- receiving, at a memory device and from a host device, a first write command;
- capturing the first write command in the memory device;
- from the memory device to the host device, sending an indication that the first write command is captured successfully;
- receiving, at the memory device and from the host device, a second write command using a first shifted data pulse from the host device;
- attempting to capture the second write command in the memory device;
- sending an indication that the attempt to capture the second write command has failed;
- and
- in response to the second write command capture failure, receiving, at the memory device and from the host device, a third write command using a second shifted data pulse from the host device, wherein the first and second shifted data pulses are shifted in opposite directions.
Dependencies are inferred from the claim text.