Circuit partitioning for a memory device

An apparatus, comprising:

• a substrate;
• a plurality of memory tiles over the substrate, each memory tile of the plurality of memory tiles comprising:
• an array layer of the memory tile located at a first distance relative to the substrate, the array layer comprising a plurality of memory cells and a plurality of access lines;
• and
• a circuit layer of the memory tile located at a second distance relative to the substrate that is nearer to or farther from the substrate than the first distance, the circuit layer comprising a first area and a second area different than the first area, the first area comprising decoder circuitry configured to selectively access the plurality of memory cells via the plurality of access lines and sensing circuitry configured to detect logic states stored by the plurality of memory cells;
• and
• data path circuitry corresponding to the plurality of memory tiles and configured to process data communicated between the plurality of memory tiles and an input/output component of the apparatus, wherein the data path circuitry is distributed across the second area of the circuit layer of two or more memory tiles of the plurality of memory tiles.

An apparatus, comprising:

• a substrate;
• a plurality of memory tiles over the substrate that each comprise a respective array of memory cells, wherein each of the plurality of memory tiles comprises a respective circuit layer located nearer to or farther from the substrate than the respective array of memory cells, the circuit layer comprising a first area and a second area different than the first area, the first area comprising circuitry configured to operate the respective array of memory cells;
• and
• circuitry for communicating data between the memory cells of the plurality of memory tiles and an input/output component, the circuitry for communicating the data distributed across the second area of the circuit layer of two or more of the plurality of memory tiles.