Method, apparatus and electronic device for controlling memory access

An apparatus for controlling access to a memory including a plurality of memory modules configured in parallel, comprising:

• an instruction parsing unit, for parsing an access instruction including an addressing field which comprises a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an address within a memory module;
• a module determining unit, for determining one or more memory modules to be accessed based on the parallel control field and the module address field;
• and
• an access performing unit, for carrying out the access to the one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field,
• wherein the parallel control field comprises a module quantity field indicating a number of memory modules to be parallelly accessed and a stride field indicating an interval among the plurality of memory modules to be accessed, and
• wherein the module determining unit is further configured to determine the one or more memory modules to be accessed beginning at a memory module assigned by the module address field and having the interval indicated by the stride field and having the number assigned by the module quantity field as the one or more memory modules to be accessed.

An electronic device, comprising:

• a processor;
• and
• a first memory including program instructions stored thereon which when executed by the processor cause the processor to perform a method for controlling access to a second memory including a plurality of memory modules configured in parallel, the method comprising:
• receiving an access instruction including an addressing field which comprises a parallel control field for controlling a parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an address within a memory module;
• parsing the access instruction to determine the parallel control field, the module address field and the in-module address field;
• determining one or more memory modules to be accessed based on the parallel control field and the module address field;
• and
• accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field,
• wherein the parallel control field comprises a module quantity field indicating a number of memory modules to be parallelly accessed and a stride field indicating an interval among the plurality of memory modules to be accessed, and
• wherein determining the one or more memory modules to be accessed based on the parallel control field and the module address field comprises:
• determining the one or more memory modules to be accessed beginning at a memory module assigned by the module address field and having the interval indicated by the stride field and having the number assigned by the module quantity field as the one or more memory modules to be accessed.

One or more non-transitory computer-readable storage media, including program instructions stored thereon that when executed by a processor cause the processor to perform a method for controlling access to a memory including a plurality of memory modules configured in parallel, the method comprising:

• receiving an access instruction including an addressing field which comprises a parallel control field for controlling a parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an address within a memory module;
• parsing the access instruction to determine the parallel control field, the module address field and the in-module address field;
• determining one or more memory modules to be accessed based on the parallel control field and the module address field;
• and
• accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field,
• wherein the parallel control field comprises a module quantity field indicating a number of memory modules to be parallelly accessed and a stride field indicating an interval among the plurality of memory modules to be accessed, and
• wherein determining the one or more memory modules to be accessed based on the parallel control field and the module address field comprises:
• determining the one or more memory modules to be accessed beginning at a memory module assigned by the module address field and having the interval indicated by the stride field and having the number assigned by the module quantity field as the one or more memory modules to be accessed.