Optimizing power usage by factoring processor architectural events to PMU

A system comprising:

• a plurality of last level cache (LLC) regions;
• a plurality of cores coupled to one or more of the LLC regions, wherein the plurality of LLC regions comprises at least four LLC regions;
• a memory interface circuit comprising a memory controller to couple the cores to a dynamic random-access memory;
• an accelerator interface to couple one or more of the cores to a graphics accelerator;
• wherein a first core of the plurality of cores comprises:
• a plurality of thermal sensors to collect thermal data for the first core, and
• a plurality of performance counters to count architectural events within the first core, including counters to count completed instructions, cache-related misses, and branch misses;
• and
• a power management unit to manage power usage on a per core basis based on at least one of available power, the thermal data from the plurality of thermal sensors, and the architectural events counted by the performance counters, and to scale up a first frequency of the first core when the architectural events indicate performance of the core is below a system bound and to enter a turbo mode for the first core based on the available power, wherein values of the performance counters are compared to respective thresholds to manage the power usage, and wherein below the system bound is indicated by the completed instruction count being below its threshold, the cache-related misses being below its threshold, and the branch miss count being above its threshold.