Efficient performance monitoring of integrated circuit(s) having distributed clocks

An integrated circuit device comprising:

• a plurality of clock domains each with a corresponding local clock;
• a plurality of performance monitors each operating in a different clock domain;
• and
• a central dispatcher coupled to a reference clock, the central dispatcher configured to:
• broadcast a trigger signal to the plurality of performance monitors,
• form a reference packet indicating when the central dispatcher broadcasted the trigger signal to the plurality of performance monitors, wherein the reference packet includes a first identification of the trigger signal and a reference clock value from the reference clock, and
• save the reference packet in a memory,
• wherein each of the performance monitors is adapted to:
• respond to the trigger signal by forming a return packet to be saved in the memory;
• and
• respond to the trigger signal by resetting one or more local performance counts;
• and
• wherein the clock domains in which the plurality of performance monitors operate are correlated based on the return packets saved in the memory and the reference clock value included in the reference packet saved in the memory.