Systems and methods for dynamic configuration of a device clock
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorsNir Ofir, Jonatan Bar-Asher, Dror Egozi, Erez Diamant
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Abstract
This disclosure describes a programmable clock configuration block disposed at the SoC system, which manages clock frequency change flow in a single clock domain on a SoC system to provide dynamic clock frequency configuration while the SoC system is in operation. The programmable clock configuration block is configured to interact with the CPU of the SoC system to configure or change parameters relating to the clock signal frequency while the CPU is in an inactive state.
Claims20
A method for dynamically configuring a frequency of a system clock signal in an integrated circuit device while the integrated circuit device is in operation, the method comprising:
- receiving, via an advanced extensible interface (AXI) bus that is uncoupled from sample-at-reset pads of the integrated circuit device, while the integrated circuit device is in operation according to a previously configured clock signal having a first frequency, a set of clock configuration parameters issued by a processor of the integrated circuit device, wherein the sample-at-reset pads is configured to provide pre-defined set of clock frequencies;
- in response to a signal issued by the processor of the integrated circuit device notifying that the integrated circuit device has entered an inactive state, configuring, via the AXI bus, a clock circuit to generate an updated clock signal for at least one clock domain within the integrated circuit device using the set of received clock configuration parameters regardless of the pre-defined set of clock frequencies, the updated clock signal having a second frequency different from the first frequency;
- and
- setting a release command to release the integrated circuit device from the inactive state thereby causing the at least one clock domain within the integrated circuit device to resume operation at the second frequency.
An electronic device having reconfigurable frequency clocks, comprising:
- a processor configured to issue and send, via an advanced extensible interface (AXI) bus that is uncoupled from sample-at-reset pads of the electronic device and to a programmable AXI module, a set of clock configuration parameters, while the electronic device is in operation according to a previously configured clock signal having a first frequency;
- the programmable AXI module configured to:
- in response to a signal issued by the processor notifying that the electronic device has entered an inactive state, configure, via the AXI bus, a clock circuit to generate an updated clock signal for at least one clock domain within the electronic device using the set of received clock configuration parameters, the updated clock signal having a second frequency different from the first frequency, and
- set a release command to release the electronic device from the inactive state thereby causing the at least one clock domain within the integrated circuit device to resume operation at the second frequency.
Dependencies are inferred from the claim text.