Dynamic maximum frequency limit for processing core groups

A system comprising:

• a memory to store instructions;
• a first processor core coupled to the memory;
• a second processor core;
• one or more circuitries to:
• assign a first maximum frequency limit to the first processor core, and
• assign a second maximum frequency limit to the second processor core, the second maximum frequency being different from the first maximum frequency, wherein the first maximum frequency limit is higher than a baseline maximum frequency limit for the first and second processor cores, and wherein the second maximum frequency limit is lower than the baseline maximum frequency limit for the first and second processor cores;
• wherein the baseline frequency limit is a function of a number of processor cores in a group, wherein the first processor core is in a first group of processor cores, wherein the second processor core is in a second group of processor cores, and wherein a number of processor cores in the first and second groups is set dynamically,
• wherein the one or more circuitries is to assign the first processor core to the first group of processor cores, based at least in part on a first workload with higher QoS than a second workload with lower QoS, which is assigned to the second processor core;
• and
• a wireless interface to allow one or both the first or second processor cores to communicate with another system.

An apparatus comprising:

• a plurality of components including first and second components;
• first one or more circuitries to perform one or both of:
• receive a plurality of parameters associated with workload assignment for the plurality of components, or
• receive a plurality of requested frequencies respectively for the plurality of components;
• and
• second one or more circuitries to assign respective maximum frequency limits to individual components of the plurality of components;
• wherein:
• the first one or more circuitries are to group the plurality of components into two or more groups;
• the second one or more circuitries are to assign, to one or more components of a first group of the two or more groups, a first maximum frequency limit, and to assign one or more components of a second group of the two or more groups, a second maximum frequency limit;
• the first maximum frequency limit is higher than a baseline maximum frequency limit for the one or more components, and
• the second maximum frequency limit is lower than the baseline maximum frequency limit for the first and second components,
• wherein a number of components in the first and second groups is set dynamically, wherein the second one or more circuitries is to assign the first component to the first group of components, based at least in part on a first workload with higher QoS than a second workload with lower QoS, which is assigned to the second component.

One or more non-transitory computer-readable storage media configured to store instructions that, when executed by a processor included in an apparatus, cause the processor to perform operations comprising:

• assign a first component to a first group of components and a second component to a second group of components;
• assign a first maximum frequency limit to the first group of components and a second maximum frequency limit to the second group of components;
• and
• cause to operate the first component and the second component, respectively, in accordance with the first maximum frequency limit and the second maximum frequency limit;
• wherein the first maximum frequency limit is higher than a baseline maximum frequency limit for the first and second components, and
• wherein the second maximum frequency limit is lower than the baseline maximum frequency limit for the first and second components,
• wherein a number of components in the first and second groups is set dynamically,
• wherein the first component is assigned to the first group of components, based at least in part on a first workload with higher QoS than a second workload with lower QoS, which is assigned to the second component.

A multiprocessor system-on-chip (SOC) with a baseline frequency limit, the multiprocessor SOC comprising:

• a first processor core to operate at a first maximum frequency limit which is higher than the baseline frequency limit;
• a second processor core to operate at a second maximum frequency limit which is lower than the baseline frequency limit, wherein the first processor core has a higher workload compared to a workload of the second processor core;
• and
• a circuitry to dynamically and adaptively assign the first processor core the first maximum frequency limit and the second processor core the second maximum frequency limit;
• wherein the baseline frequency limit is a function of a number of processor cores in a group, wherein the first processor core is in a first group, and wherein the second processor core is in a second group;
• and
• wherein the number of processor cores in a group is set dynamically;
• wherein the circuitry is to assign the first processor core to the first group, based at least in part on a first workload with higher QoS than a second workload with lower QoS, which is assigned to the second processor core.