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US 11,144,081 B2Granted
Bandgap voltage generating apparatus and operation method thereof
AssigneeHimax Technologies Limited
InventorYu-Hsuan Liu
Life of this patent
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Abstract
A bandgap voltage generating apparatus and an operation method thereof are provided. The bandgap voltage generating apparatus includes a bandgap circuit, a frequency dividing circuit, and a logic circuit. The bandgap circuit is configured to determine whether to generate a bandgap voltage based on an enable clock. The frequency dividing circuit is configured to divide an original clock to generate at least one divided clock. The logic circuit is coupled to the frequency dividing circuit and the bandgap circuit. The logic circuit uses at least one of the at least one divided clock to generate the enable clock for an enable terminal of the bandgap circuit.
Claims13
A bandgap voltage generating apparatus comprising:
- a bandgap circuit configured to determine whether to generate a bandgap voltage based on an enable clock;
- a frequency dividing circuit configured to divide an original clock to generate at least one divided clock;
- a logic circuit coupled to the frequency dividing circuit and the bandgap circuit, wherein the logic circuit uses at least one of the at least one divided clock to generate the enable clock for an enable terminal of the bandgap circuit;
- and
- a switch having a first terminal coupled to an output terminal of the bandgap circuit to receive the bandgap voltage;
- wherein the logic circuit further uses at least two of the original clock and the at least one divided clock to generate a switch clock for a control terminal of the switch;
- wherein the logic circuit comprises:
- a first NAND gate having a first input terminal configured to receive a reset signal, wherein a second input terminal of the first NAND gate is configured to receive one of the original clock and the at least one divided clock;
- and
- a second NAND gate having a first input terminal coupled to an output terminal of the first NAND gate, wherein a second input terminal of the second NAND gate is coupled to the frequency dividing circuit to receive one of the at least one divided clock, and an output ten iinal of the second NAND gate is coupled to the control terminal of the switch to provide the switch clock;
- wherein at least one of the divided clock transmitted to the second input terminal of the second NAND gate is used as the enable clock.
8 more elements
A bandgap voltage generating apparatus comprising:
- a bandgap circuit configured to determine whether to generate a bandgap voltage based on an enable clock;
- a frequency dividing circuit configured to divide an original clock to generate at least one divided clock;
- a logic circuit coupled to the frequency dividing circuit and the bandgap circuit, wherein the logic circuit uses at least one of the at least one divided clock to generate the enable clock for an enable terminal of the bandgap circuit;
- and
- a switch having a first terminal coupled to an output terminal of the bandgap circuit to receive the bandgap voltage;
- wherein the logic circuit further uses at least two of the original clock and the at least one divided clock to generate a switch clock for a control terminal of the switch;
- wherein the logic circuit comprises:
- a NAND gate having a first input terminal configured to receive a reset signal, wherein a second input terminal of the NAND gate is configured to receive one of the original clock and the at least one divided clock;
- and
- an AND gate having a first input terminal coupled to an output terminal of the NAND gate, wherein a second input terminal of the AND gate is coupled to the frequency dividing circuit to receive one of the at least one divided clock, and an output terminal of the AND gate is coupled to the control terminal of the switch to provide the switch clock;
- wherein at least one of the divided clock transmitted to the second input terminal of the AND gate is used as the enable clock.
8 more elements
An operation method of a bandgap voltage generating apparatus, comprising:
- determining, by a bandgap circuit, whether to generate a bandgap voltage based on an enable clock;
- dividing, by a frequency dividing circuit, an original clock to generate at least one divided clock;
- using, by a logic circuit, at least one of the at least one divided clock to generate the enable clock for an enable terminal of the bandgap circuit;
- and
- using at least two of the original clock and the at least one divided clock to generate a switch clock for a control terminal of a switch by the logic circuit, wherein a first terminal of the switch is coupled to an output terminal of the bandgap circuit to receive the bandgap voltage;
- wherein the logic circuit comprises:
- a first NAND gate having a first input terminal configured to receive a reset signal, wherein a second input teiminal of the first NAND gate is configured to receive one of the original clock and the at least one divided clock;
- and
- a second NAND gate having a first input terminal coupled to an output terminal of the first NAND gate, wherein a second input terminal of the second NAND gate is coupled to the frequency dividing circuit to receive one of the at least one divided clock, and an output terminal of the second NAND gate is coupled to the control terminal of the switch to provide the switch clock;
- wherein at least one of the divided clock transmitted to the second input terminal of the second NAND gate is used as the enable clock.
7 more elements
Dependencies are inferred from the claim text.