Method and apparatus for testing a multi-die integrated circuit device

Testing apparatus for scan chain testing of a multi-chip module including a plurality of integrated circuit dice, at least two of the integrated circuit dice being of a same first type and at least one of the integrated circuit dice being of a second type different from the first type, each respective integrated circuit die having a respective test access port, the testing apparatus comprising:

• a test interface that couples to each respective test access port;
• and
• a controller configured to:
• separately apply, via the test interface, a first boundary scan test stream to a respective test access port of each integrated circuit die of the first type of integrated circuit dice, the separately applying including configuring the first boundary scan test stream to test each integrated circuit die of the first type of integrated circuit dice in both transmit and receive directions by simulating loopback of transmit and receive pins of the respective integrated circuit die of the first type of integrated circuit dice;
• and
• separately apply, via the test interface, a second boundary scan test stream to a respective test access port of each integrated circuit die of the second type of integrated circuit dice, the separately applying including configuring the second boundary scan test stream to test each integrated circuit die of the second type of integrated circuit dice in both transmit and receive directions by simulating loopback of transmit and receive pins of the respective integrated circuit die of the second type of integrated circuit dice.

A multi-chip module comprising:

• a plurality of integrated circuit dice, each respective integrated circuit die comprising a respective boundary scan register chain and a respective test access port for the respective boundary scan register chain of the respective integrated circuit die;
• a test access port for testing of a boundary scan register chain spanning the multi-chip module as a whole;
• and
• a plurality of input/output pins;
• wherein:
• a first subset of the plurality of input/output pins includes first pins configurable for use for run-time functional signals during run-time operation of the multi-chip module, and configurable in a test mode as pins of a device-wide test access port;
• and
• a second subset of the plurality of input/output pins, separate from the first subset of the plurality of input/output pins, the second subset of the plurality of input/output pins including second pins configurable for use for run-time functional signals during run-time operation of the multi-chip module, and configurable in the test mode as pins of respective individual test access ports for each of the respective integrated circuit dice.