Energy efficient processor core architecture for image processor
AssigneeGoogle Inc.
InventorsAlbert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
Life of this patent
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Abstract
An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Claims20
A system comprising:
- one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
- receiving an input program to be executed on a device comprising:
- a plurality of random access memories, and
- a plurality of execution lanes, wherein different groups of the execution lanes are assigned to use a different respective random access memory of the plurality of random access memories;
- determining that the input program specifies two or more execution lanes in a same group of the plurality of execution lanes to compete for different memory locations in a same random access memory of the plurality of random access memories;
- and
- in response, modifying the input program to generate multiple instructions that cause execution lanes within each group to access a respective random access memory sequentially.
A method comprising:
- receiving an input program to be executed on a device comprising:
- a plurality of random access memories, and
- a plurality of execution lanes, wherein different groups of the execution lanes are assigned to use a different respective random access memory of the plurality of random access memories;
- determining that the input program specifies two or more execution lanes in a same group of the plurality of execution lanes to compete for different memory locations in a same random access memory of the plurality of random access memories;
- and
- in response, modifying the input program to generate multiple instructions that cause execution lanes within each group to access a respective random access memory sequentially.
Dependencies are inferred from the claim text.