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US 11,134,788 B2Granted
Multi-stage memory sensing
AssigneeMicron Technology, Inc.
InventorsHuy T. Vo, Adam S. El-Mansouri
Life of this patent
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Abstract
Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
Claims20
A method, comprising:
- precharging, during a sense operation for a memory cell, an amplifier capacitor to a first voltage, the amplifier capacitor coupled with a transistor;
- precharging a digit line coupled with the transistor to a first sensing voltage based at least in part on the digit line being coupled with the amplifier capacitor via the transistor;
- asserting a word line signal to couple the memory cell with the digit line, wherein a charge stored on the memory cell is discharged onto the digit line based at least in part on asserting the word line signal;
- deasserting, overlapping with or after asserting the word line signal, a control signal associated with the transistor to isolate the amplifier capacitor from the digit line;
- reasserting the control signal, after deasserting the control signal, to couple the digit line with the amplifier capacitor;
- and
- latching the charge on the digit line at a sense amplifier coupled with the amplifier capacitor based at least in part on reasserting the control signal.
4 more elements
A method, comprising:
- precharging, during a sense operation for a memory cell, an amplifier capacitor to a first voltage, wherein the amplifier capacitor is coupled with a first transistor coupled with a second transistor;
- precharging a digit line coupled with the second transistor to a first sensing voltage based at least in part on the digit line being coupled with the amplifier capacitor via the first transistor and the second transistor;
- asserting a word line signal to couple the memory cell with the digit line, wherein a charge stored on the memory cell is discharged onto the digit line based at least in part on asserting the word line signal;
- deasserting, overlapping with or after asserting the word line signal, a control signal associated with the first transistor to isolate the amplifier capacitor from the digit line;
- reasserting the control signal, after deasserting the control signal, to couple the digit line with the amplifier capacitor;
- and
- latching the charge on the digit line at a sense amplifier coupled with the amplifier capacitor based at least in part on reasserting the control signal.
4 more elements
An apparatus, comprising:
- a memory cell coupled with a switching component operable to be controlled by a word line signal;
- a digit line coupled with the switching component;
- a transistor coupled with the digit line and operable to be activated by a control signal;
- an amplifier capacitor coupled with the transistor;
- a sense amplifier coupled with the amplifier capacitor;
- and
- a controller configured to:
- precharge, during a sense operation for the memory cell, the amplifier capacitor to a first voltage;
- precharge the digit line to a first sensing voltage based at least in part on the digit line being coupled with the amplifier capacitor via the transistor;
- assert the word line signal to couple the memory cell with the digit line, wherein the memory cell is configured to discharge a charge onto the digit line based at least in part on asserting the word line signal;
- deassert the control signal to isolate the amplifier capacitor from the digit line;
- reassert the control signal, after deasserting the control signal, to couple the digit line with the amplifier capacitor;
- and
- latch the charge on the digit line at the sense amplifier based at least in part on reasserting the control signal.
11 more elements
Dependencies are inferred from the claim text.