Nonvolatile memory cells having an embedded selection element and nonvolatile memory cell arrays including the nonvolatile memory cells
AssigneesSK hynix Inc., Sang Min Lee
InventorSang Min Lee
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory cell includes a semiconductor layer including a first recess and a second recess. A first gate insulation layer is disposed on a bottom surface and side surfaces of the first recess. A second gate insulation layer is disposed on a bottom surface and side surfaces of the second recess. A variable resistive material layer is disposed on a first region of the semiconductor layer disposed between the first and second recesses. An insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer. A gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.
Claims19
A nonvolatile memory cell comprising:
- a semiconductor layer including a first recess and a second recess;
- a first gate insulation layer disposed on a bottom surface and side surfaces of the first recess;
- a second gate insulation layer disposed on a bottom surface and side surfaces of the second recess;
- a variable resistive material layer disposed on a first region of the semiconductor layer disposed between the first and second recesses;
- an insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer;
- and
- a gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.
A nonvolatile memory cell comprising:
- a gate terminal, a source terminal and a drain terminal coupled to a word line, a source line and a bit line, respectively;
- a resistor coupled between the source terminal and the drain terminal and comprised of a variable resistive material layer;
- a first channel region provided between the resistor and the source terminal;
- and
- a second channel region provided between the resistor and the drain terminal,
- wherein whether a first channel and a second channel are formed in the first and second channel regions, respectively, is determined according to a word line voltage applied to the word line.
A nonvolatile memory cell array comprising:
- a first word line coupled to a first unit cell and a second unit cell;
- a second word line coupled to a third unit cell and a fourth unit cell;
- a first source line coupled to the first and third unit cells;
- a second source line coupled to the second and fourth unit cells;
- and
- a bit line coupled to the first to fourth unit cells,
- wherein each of the first to fourth unit cells includes:
- a gate terminal coupled to any one of the first and second word lines;
- a source terminal coupled to any one of the first and second source lines;
- a drain terminal coupled to the bit line;
- a resistor coupled between the source terminal and the drain terminal and comprised of a variable resistive material layer;
- a first channel region provided between the resistor and the source terminal;
- and
- a second channel region provided between the resistor and the drain terminal,
- wherein whether a first channel and a second channel are formed in the first and second channel regions, respectively, is determined according to a voltage applied to the gate terminal.
Dependencies are inferred from the claim text.