# US 11,122,678 B2 · Packaged device having imbedded array of components > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,122,678 B2 - Document ID: US11122678B2 - Status: Granted - Kind: B2 - Application number: 16/735,573 - Filed: 2020-01-06 - Published: 2020-07-09 - Granted: 2021-09-14 - Earliest claimed: 2019-01-07 - Assignees: Tesla, Inc. - Applicants: Tesla, Inc. - Inventors: Vijaykumar Krithivasan; Jin Zhao; Mengzhi Pang; Steven Wayne Butler; Ganesh Venkataramanan; Yang Sun - Web page: https://patentgrep.com/patent/US11122678B2 ## CPC - G06F 1/20: Cooling means - H05K 1/023: {using auxiliary mounted passive components or auxiliary substances (printed passive components H05K1/16)} - G06F 1/183: Internal mounting support structures, e.g. for supporting printed circuit boards - H05K 1/0224: {Patterned shielding planes, ground planes or power planes (H05K1/0253 takes precedence)} - H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards - H05K 3/301: {by means of a mounting structure (H05K3/325 takes precedence)} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H05K 1/0231: {Capacitors or dielectric substances} - H05K 1/0263: {High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board (H05K1/0293 takes precedence)} - H05K 1/141: {One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence)} - H05K 1/181: associated with surface mounted components - H05K 2201/0792: Means against parasitic impedance; Means against eddy currents - H05K 2201/10515: Stacked components - H05K 2201/1053: Mounted components directly electrically connected to each other, i.e. not via the PCB - H05K 2201/10545: Related components mounted on both sides of the PCB - H05K 2201/10636: Leadless chip, e.g. chip capacitor or resistor - H05K 2201/10674: Flip chip - H10W 40/10: Arrangements for heating - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer. ## Claims ### Claim 1 A structure comprising: an imbedded component array layer having a plurality of imbedded passive devices contained therein; an Integrated Fanout (InFO) layer residing adjacent a first surface of the imbedded component array layer having a plurality of traces and a plurality of vias formed therein, the InFO layer comprising a plurality of conductors electrically connecting the plurality of imbedded passive devices; an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer, wherein the insulator layer has a plurality of solder balls formed therein; and a plurality of vias passing through the imbedded component array layer and electrically coupled to: some of the plurality of vias of the InFO layer, and the plurality of solder balls, thereby electrically coupling the insulator layer to the imbedded component array layer. ### Claim 2 (depends on 1) The structure of claim 1, further comprising: different solder balls providing electrical connections to the InFO layer, wherein the plurality solder balls provide electrical connections to the plurality of vias passing through the imbedded component array layer. ### Claim 3 (depends on 1) The structure of claim 1, wherein the array of components includes at least one of: lumped capacitors; lumped inductors; lumped resistors; or Integrated Circuits (ICs). ### Claim 4 A structure comprising: a first imbedded component array layer having a first array of imbedded passive devices contained therein; a second imbedded component array layer having a second array of imbedded passive devices contained therein; a first Integrated Fanout (InFO) layer residing adjacent a first surface of the first imbedded component array layer having a first plurality of traces and a second plurality of vias formed therein, the first InFO layer comprising a plurality of conductors electrically connecting the first array of imbedded passive devices; a second InFO layer residing adjacent a first surface of the second imbedded component array layer having a second plurality of traces and a second plurality of vias formed therein, the second InFO layer comprising a plurality of conductors electrically connecting the second array of imbedded passive devices; a connectivity layer residing adjacent a second surface of the first imbedded component array layer and adjacent a second surface of the second imbedded component array layer such that the connectivity layer is sandwiched between the first imbedded component array layer and the second imbedded component array layer, the connectivity layer having a third plurality of traces and a third plurality of vias formed therein; a first plurality of vias passing through the first imbedded component array layer; and a second plurality of vias passing through the second imbedded component array layer. ### Claim 5 (depends on 4) The structure of claim 4, further comprising: first solder balls providing electrical connections to the first InFO layer; and second solder balls providing electrical connections to second InFO layer. ### Claim 6 (depends on 4) The structure of claim 4, wherein the array of components includes at least one of: lumped capacitors; lumped inductors; lumped resistors; or Integrated Circuits (ICs). ### Claim 7 A Printed Circuit Board (PCB) comprising: a first core; a first array of components formed in the first core, wherein the first array of components is mounted in etched portions of the first core; a second core; a second array of components formed in the second core; a plurality of conductors intercoupled to the first array of components; a plurality of conductors coupled to the second array of components; and a plurality of conductors that provide signal routing external to the PCB. ### Claim 8 (depends on 7) The PCB of claim 7, further comprising a plurality of conductors that provide electrical shielding. ### Claim 9 (depends on 7) The PCB of claim 7, wherein the plurality of conductors coupled to the first array of components provide connections to a plurality of components external to the PCB. ### Claim 10 (depends on 7) The PCB of claim 7, wherein the first array of components includes at least one of: lumped capacitors; lumped inductors; lumped resistors; or Integrated Circuits (ICs). ### Claim 11 A method for constructing a Printed Circuit Board (PCB) comprising: forming a first core via etching portions of the first core, wherein a first array of components is mounted in the etched portions of the first core; forming a second core having a second array of components dispersed therein; forming a plurality of conductors intercoupled to the first array of components; forming a plurality of conductors coupled to the second array of components; and forming a plurality of conductors that provide signal routing external to the PCB. ### Claim 12 (depends on 11) The method of claim 11, further comprising forming a plurality of conductors that provide electrical shielding. ### Claim 13 (depends on 11) The method of claim 11, wherein the plurality of conductors coupled to the first array of components provide connections to a plurality of components external to the PCB. ### Claim 14 (depends on 11) The method of claim 11, wherein the first array of components includes at least one of: lumped capacitors; lumped inductors; lumped resistors; or Integrated Circuits (ICs).