# US 11,122,674 B1 · PCB with coin and dielectric layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,122,674 B1 - Document ID: US11122674B1 - Status: Granted - Kind: B1 - Application number: 16/946,711 - Filed: 2020-07-01 - Granted: 2021-09-14 - Earliest claimed: 2020-05-15 - Applicants: Multek Technologies Limited - Inventors: Pui Yin Yu; Xin Hua Zeng; Jian Ying Xue; Hong Tu Zhang - Web page: https://patentgrep.com/patent/US11122674B1 ## CPC - H05K 1/0204: {using means for thermal conduction connection in the thickness direction of the substrate (H05K1/0207 takes precedence)} - H05K 1/021: {Components thermally connected to metal substrates or heat-sinks by insert mounting} - H05K 1/183: associated with components mounted in and supported by recessed areas of the PCBs - H05K 3/0061: {onto a metallic substrate, e.g. a heat sink (heat sinks for electric apparatus H05K7/20)} - H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)} - H05K 3/0044: {Mechanical working of the substrate, e.g. drilling or punching (H05K3/0008 takes precedence)} - H05K 3/424: {by direct electroplating} - H05K 2201/0338: Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer - H05K 2201/10416: Metallic blocks or heatsinks completely inserted in a PCB - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A printed circuit board includes a first, second, and third conductive layer. The printed circuit boards also includes a first non-conductive layer between the first and second conductive layers and a second non-conductive layer between the second and third conductive layers. The printed circuit board further includes a dielectric layer between the second conductive layer and the second non-conductive layer and a coin for heat dispersion located underneath the dielectric layer. The printed circuit board also includes a cavity for receiving a component and a plating within the cavity to connect the coin with the second conductive layer. The plating extends less than 50 um above the second conductive layer. ## Claims ### Claim 1 A printed circuit board comprising: a first, second, and third conductive layer; a first non-conductive layer between the first and second conductive layers; a second non-conductive layer between the second and third conductive layers; a dielectric layer between the second conductive layer and the second non-conductive layer; a coin for heat dispersion located underneath the dielectric layer; a cavity for receiving a component; and a plating within the cavity to connect the coin with the second conductive layer, wherein the plating extends less than 50 um above the second conductive layer. ### Claim 2 (depends on 1) The printed circuit board of claim 1, further comprising a via. ### Claim 3 (depends on 2) The printed circuit board of claim 2, wherein the via has a plating to connect one or more conductive layers. ### Claim 4 (depends on 3) The printed circuit board of claim 3, wherein the plating is copper. ### Claim 5 (depends on 1) The printed circuit board of claim 1, wherein the plating extends between 0.1 um and 50 um. ### Claim 6 (depends on 1) The printed circuit board of claim 1, further comprising a fourth conductive layer and a third non-conductive layer between the third and fourth conductive layer. ### Claim 7 (depends on 1) The printed circuit board of claim 1, wherein the dielectric layer is between 1 and 40 um thick. ### Claim 8 (depends on 1) The printed circuit board of claim 1, wherein the dielectric layer eliminates a need for electroless copper plating to electrically couple the second conductive layer and the coin because the dielectric layer enables electrolytically added copper plating to grow directly across it. ### Claim 9 (depends on 1) The printed circuit board of claim 1, where one of the non-conductive layers includes a prepreg. ### Claim 10 A printed circuit board comprising: a first, second, third, fourth, fifth and sixth conductive layer; a first laminate between the first and second conductive layers; a first prepreg layer between the second and third conductive layers; a dielectric layer between the first prepreg layer and the second conductive layer, the first dielectric layer having a thickness between 1 and 40 um; a second laminate between the third and fourth conductive layers; a second prepreg layer between the fourth and fifth conductive layers; a third laminate between the fifth and sixth conductive layers; a coin for heat dispersion located underneath the dielectric layer; a cavity for receiving a component above the coin; and a plating within the cavity to connect the coin with the second conductive layer, wherein the plating extends less than 50 um above the second conductive layer and wherein the dielectric layer eliminates a need for electroless copper plating to electrically couple the second conductive layer and the coin because the dielectric layer enables electrolytically added copper plating to grow directly across it. ### Claim 11 (depends on 10) The printed circuit board of claim 10 further comprising a via wherein the via has a copper plating to connect one or more conductive layers. ### Claim 12 A method of manufacturing a printed circuit board, the method comprising: laminating a multi-stack printed circuit board having first, second and third conductive layers, a first non-conductive layer between the first and second conductive layers, a second non-conductive layer between the second and third conductive layers, a dielectric layer between the second conductive layer and the second non-conductive layer, a coin underneath the dielectric layer; routing a cavity for receiving a component; and plating the cavity to connect the coin and the second conductive layer, wherein the plating extends less than 50 um above the second conductive layer. ### Claim 13 (depends on 12) The method of claim 12, wherein plating includes plating by electrolytically adding copper directly across the dielectric layer without first using electroless copper plating. ### Claim 14 (depends on 13) A method according to claim 13, further comprising using electroless copper plating to plate a first copper layer in the via. ### Claim 15 (depends on 14) A method according to claim 14 wherein the copper plating extends the whole length of the via to connect the first and third conductive layers. ### Claim 16 (depends on 12) A method according to claim 12, further comprising drilling a via in the printed circuit board. ### Claim 17 (depends on 16) A method according to claim 16, further comprising plating with copper over the first copper layer to form a second copper layer. ### Claim 18 (depends on 12) A method according to claim 12, mounting a component in the cavity after plating the cavity. ### Claim 19 (depends on 12) A method according to claim 12, wherein laminating includes a fourth conductive layer and a third non-conductive layer between the fourth conductive layer and the third conductive layer. ### Claim 20 (depends on 12) A method according to claim 12, wherein laminating includes using a prepreg.