# US 11,122,187 B2 · Transmitter, receiver, transmitter/receiver, and transmitting/receiving system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,122,187 B2 - Document ID: US11122187B2 - Status: Granted - Kind: B2 - Application number: 16/829,491 - Filed: 2020-03-25 - Published: 2020-10-01 - Granted: 2021-09-14 - Earliest claimed: 2019-03-28 - Assignees: Thine Electronics, Inc. - Applicants: Thine Electronics, Inc. - Inventors: Tomohiro Sakai; Kazuhisa Sasaki; Satoshi Miura; Daisuke Iwama - Web page: https://patentgrep.com/patent/US11122187B2 ## CPC - H04N 5/14: Picture signal circuitry for video frequency region (cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00) - G06F 3/14: Digital output to display device {; Cooperation and interconnection of the display device with other functional units} - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - H04N 21/4122: {additional display device, e.g. video projector (digital output for controlling a plurality of local displays G06F3/1423)} - H04N 21/4347: {Demultiplexing of several video streams} - H04N 21/4363: Adapting the video stream to a specific local network, e.g. a Bluetooth® network - G09G 2370/12: Use of DVI or HDMI protocol in interfaces along the display data pipeline - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract This embodiment relates to a transmitter and the like that prevent an increase of the number of cables of an external interface even when the types of signals to be transmitted increase. The transmitter includes a latch circuit, an encoder, a serializer, and a selector. The latch circuit keeps a level of each of a plurality of signals at the timing specified by a sampling clock, and then, outputs the plurality of signals as a parallel data signal. The encoder generates an encoded parallel data signal based on the parallel data signal from the latch circuit. The serializer generates a serial data signal based on the encoded parallel data signal from the encoder. The sampling clock has a frequency higher than a transmission rate of the fastest signal of the plurality of signals. ## Claims ### Claim 1 A transmitter that transmits to a receiver a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, the transmitter comprising: a latch circuit having a first input terminal that inputs the plurality of signals, a second input terminal that inputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, and an output terminal that outputs a parallel data signal, the latch circuit being configured to keep a level of each of the plurality of signals at a timing indicated by the sampling clock, and then, to output the plurality of signals as the parallel data signal; an encoder having an input terminal electrically connected to the output terminal of the latch circuit and an output terminal that outputs an encoded parallel data signal, the encoder being configured to generate the encoded parallel data signal based on the parallel data signal from the latch circuit; a serializer having an input terminal electrically connected to the output terminal of the encoder and an output terminal that outputs the serial data signal, the serializer being configured to generate the serial data signal based on the encoded parallel data signal from the encoder; and a selector having a first input terminal electrically connected to the output terminal of the serializer, a second input terminal that inputs a training pattern signal for training clock data recovery in the receiver, and an output terminal that outputs a signal to be transmitted to the receiver, the selector being configured to select any of the training pattern signal and the serial data signal from the serializer as the signal to be transmitted to the receiver. ### Claim 2 (depends on 1) The transmitter according to claim 1, wherein the sampling clock is faster than the transmission rate of the fastest signal of the plurality of signals and asynchronous with the fastest signal. ### Claim 3 (depends on 1) The transmitter according to claim 1, wherein any of the plurality of signals is an audio signal, and the sampling clock has a frequency equivalent to a transmission rate of the audio signal or a multiplied frequency. ### Claim 4 (depends on 1) The transmitter according to claim 1, wherein any of the plurality of signals is a clock embedded data signal. ### Claim 5 A receiver that receives from a transmitter a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, the receiver comprising: a receiving unit having an input terminal that inputs a training pattern signal and the serial data signal transmitted from the transmitter, a first output terminal that outputs a recovered clock, and a second output terminal that outputs recovered data, the receiving unit being configured to perform training of clock data recovery based on the training pattern signal and to recover the clock and data based on the serial data signal transmitted from the transmitter after the training is completed; a frequency divider having an input terminal electrically connected to the first output terminal of the receiving unit and an output terminal that outputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, the frequency divider being configured to divide a frequency of the recovered clock from the receiving unit so as to generate the sampling clock; a deserializer having an input terminal electrically connected to the second output terminal of the receiving unit and an output terminal that outputs a parallel data signal, the deserializer being configured to generate the parallel data signal based on the recovered data from the receiving unit; a decoder having an input terminal electrically connected to the output terminal of the deserializer and an output terminal that outputs a decoded parallel data signal, the decoder being configured to generate the decoded parallel data signal based on the parallel data signal from the deserializer; and a latch circuit having an input terminal electrically connected to the output terminal of the decoder and an output terminal that outputs any of the plurality of signals, the latch circuit being configured to keep a level of each bit of the decoded parallel data signal from the decoder at a timing indicated by the sampling clock, and then, to output a signal of each bit as any of the plurality of signals. ### Claim 6 (depends on 5) The receiver according to claim 5, wherein the sampling clock is faster than the transmission rate of the fastest signal of the plurality of signals and asynchronous with the fastest signal. ### Claim 7 (depends on 5) The receiver according to claim 5, wherein any of the plurality of signals is an audio signal, and the sampling clock has a frequency equivalent to a transmission rate of the audio signal or a multiplied frequency. ### Claim 8 (depends on 5) The receiver according to claim 5, wherein any of the plurality of signals is a clock embedded data signal. ### Claim 9 (depends on 5) A transmitting/receiving system comprising: a transmitter, and the receiver according to claim 5, the receiver being configured to receive the serial data signal transmitted from the transmitter, wherein the transmitter transmits to a receiver a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, and comprises: a latch circuit having a first input terminal that inputs the plurality of signals, a second input terminal that inputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, and an output terminal that outputs a parallel data signal, the latch circuit being configured to keep a level of each of the plurality of signals at a timing indicated by the sampling clock, and then, to output the plurality of signals as the parallel data signal; an encoder having an input terminal electrically connected to the output terminal of the latch circuit and an output terminal that outputs an encoded parallel data signal, the encoder being configured to generate the encoded parallel data signal based on the parallel data signal from the latch circuit; a serializer having an input terminal electrically connected to the output terminal of the encoder and an output terminal that outputs the serial data signal, the serializer being configured to generate the serial data signal based on the encoded parallel data signal from the encoder; and a selector having a first input terminal electrically connected to the output terminal of the serializer, a second input terminal that inputs a training pattern signal for training clock data recovery in the receiver, and an output terminal that outputs a signal to be transmitted to the receiver, the selector being configured to select any of the training pattern signal and the serial data signal from the serializer as the signal to be transmitted to the receiver. ### Claim 10 (depends on 6) A transmitting/receiving system comprising: a transmitter; and the receiver according to claim 6, the receiver being configured to receive the serial data signal transmitted from the transmitter, wherein the transmitter transmits to a receiver a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, and comprises: a latch circuit having a first input terminal that inputs the plurality of signals, a second input terminal that inputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, and an output terminal that outputs a parallel data signal, the latch circuit being configured to keep a level of each of the plurality of signals at a timing indicated by the sampling clock, and then, to output the plurality of signals as the parallel data signal; an encoder having an input terminal electrically connected to the output terminal of the latch circuit and an output terminal that outputs an encoded parallel data signal, the encoder being configured to generate the encoded parallel data signal based on the parallel data signal from the latch circuit; a serializer having an input terminal electrically connected to the output terminal of the encoder and an output terminal that outputs the serial data signal, the serializer being configured to generate the serial data signal based on the encoded parallel data signal from the encoder; and a selector having a first input terminal electrically connected to the output terminal of the serializer, a second input terminal that inputs a training pattern signal for training clock data recovery in the receiver, and an output terminal that outputs a signal to be transmitted to the receiver, the selector being configured to select any of the training pattern signal and the serial data signal from the serializer as the signal to be transmitted to the receiver, wherein the sampling clock is faster than the transmission rate of the fastest signal of the plurality of signals and asynchronous with the fastest signal. ### Claim 11 (depends on 7) A transmitting/receiving system comprising: a transmitter; and the receiver according to claim 7, the receiver being configured to receive the serial data signal transmitted from the transmitter, wherein the transmitter transmits to a receiver a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, and comprises: a latch circuit having a first input terminal that inputs the plurality of signals, a second input terminal that inputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, and an output terminal that outputs a parallel data signal, the latch circuit being configured to keep a level of each of the plurality of signals at a timing indicated by the sampling clock, and then, to output the plurality of signals as the parallel data signal; an encoder having an input terminal electrically connected to the output terminal of the latch circuit and an output terminal that outputs an encoded parallel data signal, the encoder being configured to generate the encoded parallel data signal based on the parallel data signal from the latch circuit; a serializer having an input terminal electrically connected to the output terminal of the encoder and an output terminal that outputs the serial data signal, the serializer being configured to generate the serial data signal based on the encoded parallel data signal from the encoder; and a selector having a first input terminal electrically connected to the output terminal of the serializer, a second input terminal that inputs a training pattern signal for training clock data recovery in the receiver, and an output terminal that outputs a signal to be transmitted to the receiver, the selector being configured to select any of the training pattern signal and the serial data signal from the serializer as the signal to be transmitted to the receiver, and wherein any of the plurality of signals is an audio signal, and the sampling clock has a frequency equivalent to a transmission rate of the audio signal or a multiplied frequency. ### Claim 12 (depends on 8) A transmitting/receiving system comprising: a transmitter; and the receiver according to claim 8, the receiver being configured to receive the serial data signal transmitted from the transmitter, wherein the transmitter transmits to a receiver a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, and comprises: a latch circuit having a first input terminal that inputs the plurality of signals, a second input terminal that inputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, and an output terminal that outputs a parallel data signal, the latch circuit being configured to keep a level of each of the plurality of signals at a timing indicated by the sampling clock, and then, to output the plurality of signals as the parallel data signal; an encoder having an input terminal electrically connected to the output terminal of the latch circuit and an output terminal that outputs an encoded parallel data signal, the encoder being configured to generate the encoded parallel data signal based on the parallel data signal from the latch circuit; a serializer having an input terminal electrically connected to the output terminal of the encoder and an output terminal that outputs the serial data signal, the serializer being configured to generate the serial data signal based on the encoded parallel data signal from the encoder; and a selector having a first input terminal electrically connected to the output terminal of the serializer, a second input terminal that inputs a training pattern signal for training clock data recovery in the receiver, and an output terminal that outputs a signal to be transmitted to the receiver, the selector being configured to select any of the training pattern signal and the serial data signal from the serializer as the signal to be transmitted to the receiver, and wherein any of the plurality of signals is a clock embedded data signal. ### Claim 13 (depends on 9) The transmitting/receiving system according to claim 9, wherein, in the transmitter, the sampling clock is faster than the transmission rate of the fastest signal of the plurality of signals and asynchronous with the fastest signal. ### Claim 14 (depends on 9) The transmitting/receiving system according to claim 9, wherein, in the transmitter, any of the plurality of signals is an audio signal, and the sampling clock has a frequency equivalent to a transmission rate of the audio signal or a multiplied frequency. ### Claim 15 (depends on 9) The transmitting/receiving system according to claim 9, wherein, in the transmitter, any of the plurality of signals is a clock embedded data signal. ### Claim 16 (depends on 9) The transmitting/receiving system according to claim 9, wherein, in the receiver, the sampling clock is faster than the transmission rate of the fastest signal of the plurality of signals and asynchronous with the fastest signal. ### Claim 17 (depends on 9) The transmitting/receiving system according to claim 9, wherein, in the receiver, any of the plurality of signals is an audio signal, and the sampling clock has a frequency equivalent to a transmission rate of the audio signal or a multiplied frequency. ### Claim 18 (depends on 9) The transmitting/receiving system according to claim 9, wherein, in the receiver, any of the plurality of signals is a clock embedded data signal. ### Claim 19 (depends on 11) The transmitting/receiving system according to claim 11, further comprising: a video transmitter configured to transmit a video signal; and a video receiver configured to receive a video signal transmitted from the video transmitter.