# US 11,121,933 B2 · Physically aware topology synthesis of a network

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,121,933 B2
- Document ID: US11121933B2
- Status: Granted
- Kind: B2
- Application number: 16/728,335
- Filed: 2019-12-27
- Published: 2021-07-01
- Granted: 2021-09-14
- Earliest claimed: 2019-12-27
- Assignees: Arteris, Inc.
- Applicants: Arteris, Inc.
- Inventors: Moez Cherif; Benoit De Lescure
- Web page: https://patentgrep.com/patent/US11121933B2

## CPC

- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/32: Circuit design at the digital level (reconfigurable circuits G06F30/34)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H04L 41/0803: Configuration setting
- H04L 41/12: Discovery or management of network topologies
- H04L 41/145: {involving simulating, designing, planning or modelling of a network}
- H04L 43/0811: by checking connectivity
- H04L 43/0876: Network utilisation, e.g. volume of load or congestion level
- H04L 45/46: {Cluster building}
- H04L 49/109: Integrated on microchip, e.g. switch-on-chip
- H04L 67/1001: for accessing one among a plurality of replicated servers
- H04L 69/329: in the application layer [OSI layer 7]
- H04W 40/32: for defining a routing cluster membership
- H04W 84/18: Self-organising networks, e.g. ad-hoc networks or sensor networks
- G06F 2115/02: System on chip [SoC] design
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

System and methods are disclosed for synthesis of network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.

## Claims

### Claim 1

A method for synthesis and generation of a network-on-chip (NoC), the method comprising:
receiving a plurality of physical constraints for the NoC;
receiving a plurality of performance constraints for the NoC; and
generating a network description for the NoC using the plurality of physical constraints and the plurality of performance constraints, wherein the network description satisfies the plurality of physical constraints and the plurality of performance constraints;
generating a global consolidation roadmap including connectivity between a plurality of initiators and a plurality of targets;
creating a main node per traffic class;
decomposing the main node into mergers and splitters;
decomposing the mergers into a plurality of merger cascades;
decomposing the splitters into a plurality of splitter cascades;
physically distributing a first group of the splitter cascades selected from the plurality of splitter cascaded and a first group of the merger cascades selected from the plurality of merger cascaded on the global consolidation roadmap;
physically distributing a second group of the splitter cascades selected from the plurality of splitter cascaded and a second group of the merger cascades selected from the plurality of merger cascaded on the global consolidation roadmap;
merging at least two nodes, which are selected from a plurality of nodes, using performance-aware node clustering; and
clustering using performance aware edge clustering.

### Claim 2 (depends on 1)

The method of claim 1 further comprising providing a plurality of definitions, wherein the plurality of definitions includes clock and power domain definitions.

### Claim 3 (depends on 2)

The method of claim 2 wherein the plurality of definitions includes initiator and target connectivity.

### Claim 4 (depends on 3)

The method of claim 3 wherein each connectivity definition is labelled by traffic class.

### Claim 5 (depends on 2)

The method of claim 2 wherein the plurality of definitions includes a set of scenarios.

### Claim 6 (depends on 2)

The method of claim 2 wherein the plurality of definitions includes physical information.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
optimizing the network description; and
re-structuring the network description.

### Claim 8 (depends on 1)

The method of claim 1 further comprising performing routing and legalization of the network description.

### Claim 9 (depends on 1)

The method of claim 1, wherein the global consolidation roadmap includes:
a first roadmap between the plurality of initiators and the plurality of targets for each target receiving communication from its respective initiator; and
a second roadmap between the plurality of targets and the plurality of initiators for each initiator receiving communication from its respective target.

### Claim 10 (depends on 1)

The method of claim 1 further comprising:
generating a list of network elements for the NoC including configuration for each network element; and
positioning of each network element on a floorplan of the NoC;
locating a set of routes on the floorplan of the NoC for the connectivity between the network elements.

### Claim 11 (depends on 10)

The method of claim 10 further comprising implementing the NoC using at least one of: logic synthesis tool and place-route back end tool.

### Claim 12

A non-transitory computer readable medium for storing code, which when executed by one or more processors, would cause the processor to:
receive a plurality of physical constraints for a network-on-chip (NoC);
receive a plurality of performance constraints for the NoC and generate a network description for the NoC using the plurality of physical constraints and the plurality of performance constraints, wherein the network description satisfies the plurality of physical constraints and the plurality of performance constraints;
generate a global consolidation roadmap including connectivity between a plurality of initiators and a plurality of targets;
create a main node per traffic class;
decompose the main node into mergers and splitters;
decompose the mergers into a plurality of merger cascades;
decompose the splitters into a plurality of splitter cascades;
physically distribute a first group of the splitter cascades selected from the plurality of splitter cascaded and a first group of the merger cascades selected from the plurality of merger cascaded on the global consolidation roadmap; and
physically distribute a second group of the splitter cascades selected from the plurality of splitter cascaded and a second group of the merger cascades selected from the plurality of merger cascaded on the global consolidation roadmap;
merge nodes selected from a plurality of nodes using performance-aware node clustering; and
cluster edges using performance aware edge clustering.

### Claim 13 (depends on 12)

The non-transitory computer medium of claim 12 further comprising code that, when executed by the processor, would cause the processor to provide to a sequencer a plurality definitions selected from the group of definitions including:
clock and power domain definitions;
initiator and target connectivity in a NoC definition;
connectivity between each initiator and target pair definition, wherein each connectivity is labelled by traffic class;
a set of scenarios; and
physical information.

### Claim 14 (depends on 13)

The non-transitory computer medium of claim 13 further comprising code that, when executed by the processor, would cause the processor to:
generate a list of network elements of the NoC including configuration for each network element;
position each network element on a floorplan of the NoC;
locate a set of routes on the floorplan of the NoC representing connectivity between the network elements.
