# US 11,121,851 B2 · Differential sensing circuit for clock skew calibration relative to reference clock > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,121,851 B2 - Document ID: US11121851B2 - Status: Granted - Kind: B2 - Application number: 16/743,706 - Filed: 2020-01-15 - Published: 2021-07-01 - Granted: 2021-09-14 - Earliest claimed: 2019-12-28 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Manu Basil; Mohan Yang; Yongseon Koh; Roland Ribeiro - Web page: https://patentgrep.com/patent/US11121851B2 ## CPC - H04L 7/042: {Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15)} - H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125) - H03K 5/24: the characteristic being amplitude - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03L 7/0807: {concerning mainly a recovery circuit for the reference signal} - H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A system includes a differential clock source configured to provide a reference clock signal and an inverted version of the reference clock signal. The system also includes a quadrature clock source configured to provide a quadrature clock signal that is phase-shifted relative to the reference clock signal. The system also includes a differential sensing circuit coupled to the differential clock source and the quadrature clock source. The differential sensing circuit is configured to determine skew of the quadrature clock signal based on the reference clock signal, the inverted version of the reference clock signal, and the quadrature clock signal. ## Claims ### Claim 1 A system, comprising: a differential clock source configured to provide a reference clock signal and an inverted version of the reference clock signal; a quadrature clock source configured to provide a quadrature clock signal that is phase-shifted relative to the reference clock signal; a differential sensing circuit coupled to the differential clock source and the quadrature clock source, wherein the differential sensing circuit is configured to determine skew of the quadrature clock signal based on the reference clock signal, the inverted version of the reference clock signal, and the quadrature clock signal, wherein the differential sensing circuit comprises: a first sense circuit configured to provide a first sense signal based on the reference clock signal and the quadrature clock signal; a second sense circuit configured to provide a second sense signal based on the quadrature clock signal and the inverted version of the reference clock signal; and a comparator configured to compare the first sense signal and the second sense signal. ### Claim 2 (depends on 1) The system of claim 1, wherein the first sense circuit comprises a first NAND gate and a first low-pass filter, and wherein the second sense circuit comprises a second NAND gate and a second low-pass filter. ### Claim 3 (depends on 1) The system of claim 1, wherein an output of the comparator is used to correct the quadrature clock signal. ### Claim 4 (depends on 3) The system of claim 3, wherein a corrected quadrature clock signal is used to correct a skew of a quarter-rate clock signal, where the differential sensing circuit is configured to determine skew of the quarter-rate clock signal based on the corrected quadrature clock signal, the reference clock signal, and the quarter-rate clock signal. ### Claim 5 (depends on 4) The system of claim 4, wherein the differential sensing circuit further comprises: a first NAND gate included with the first sense circuit, wherein the first NAND gate receives the reference clock signal and the quadrature clock signal as inputs; a second NAND gate included with the second sense circuit, wherein the second NAND gate receives the quadrature clock signal and an inverted version of the reference clock signal as inputs; a third NAND gate configured to receive the corrected quadrature clock signal and the quarter-rate clock signal; a fourth NAND gate configured to receive the quarter-rate clock signal and the reference clock signal. ### Claim 6 (depends on 5) The system of claim 5, wherein the differential sensing circuit further comprises: a first switch between an output of the first NAND gate and a first low-pass filter included with the first sense circuit; a second switch between an output of the second NAND gate and a second low-pass filter included with the second sense circuit; a third switch between the output of the third NAND gate and the second low-pass filter; a fourth switch between the output of the fourth NAND gate and the first low-pass filter; and a controller coupled to the first, second, third, and fourth switches. ### Claim 7 (depends on 3) The system of claim 3, further comprising a clock and data recovery (CDR) circuit configured to perform clock recovery operations based on a corrected quadrature clock signal. ### Claim 8 A clock skew calibration circuit, comprising: a differential sensing circuit, wherein the differential sensing circuit comprises: a first sense circuit configured to provide a first sense signal based on a reference clock signal and a target clock signal that is phase-shifted relative to the reference clock signal; a second sense circuit configured to provide a second sense signal based on an inverted version of the reference clock signal and the target clock signal; and a comparator configured to compare the first sense signal and the second sense signal. ### Claim 9 (depends on 8) The clock skew calibration circuit of claim 8, wherein the first sense circuit comprises a first NAND gate and a first low-pass filter, and wherein the second sense circuit comprises a second NAND gate and a second low-pass filter. ### Claim 10 (depends on 8) The clock skew calibration circuit of claim 8, wherein the target clock signal is a quadrature clock signal, and wherein an output of the comparator is used to correct skew of the quadrature clock signal. ### Claim 11 (depends on 8) The clock skew calibration circuit of claim 8, wherein the target clock signal is a quarter-rate clock signal, and wherein an output of the comparator is used to correct skew of the quarter-rate clock signal. ### Claim 12 (depends on 8) The clock skew calibration circuit of claim 8, wherein the differential sensing circuit further comprises: a first NAND gate included with the first sense circuit, wherein the first NAND gate receives the reference clock signal and the target clock signal as inputs; and a second NAND gate included with the second sense circuit, wherein the second NAND gate receives the target clock signal and the inverted version of the reference clock signal as inputs. ### Claim 13 (depends on 12) The clock skew calibration circuit of claim 12, further comprising: a third NAND gate configured to receive a corrected target clock signal and a quarter-rate clock signal; and a fourth NAND gate configured to receive the quarter-rate clock signal and the reference clock signal. ### Claim 14 (depends on 13) The clock skew calibration circuit of claim 13, wherein the differential sensing circuit further comprises: a first switch between an output of the first NAND gate and a first low-pass filter included with the first sense circuit; a second switch between an output of the second NAND gate and a second low-pass filter included with the second sense circuit; a third switch between the output of the third NAND gate and the second low-pass filter; a fourth switch between the output of the fourth NAND gate and the first low-pass filter; and a controller coupled to the first, second, third, and fourth switches. ### Claim 15 A serializer/deserializer circuit, comprising: a clock and data recovery (CDR) circuit; a differential sensing circuit coupled to the CDR circuit, wherein the differential sensing circuit comprises: a first sense circuit configured to provide a first sense signal based on a reference clock signal and a target clock signal that is phase-shifted relative to the reference clock signal; a second sense circuit configured to provide a second sense signal based on the target clock signal and an inverted version of the reference clock signal; and a comparator configured to compare the first sense signal and the second sense signal. ### Claim 16 (depends on 15) The serializer/deserializer circuit of claim 15, wherein the first sense circuit comprises a first NAND gate and a first low-pass filter, wherein the second sense circuit comprises a second NAND gate and a second low-pass filter, wherein the target clock signal is a quadrature clock signal, and wherein an output of the comparator is used to correct skew of the quadrature clock signal. ### Claim 17 (depends on 15) The serializer/deserializer circuit of claim 15, wherein the differential sensing circuit further comprises: a first NAND gate included with the first sense circuit, wherein the first NAND gate receives the reference clock signal and the target clock signal as inputs; and a second NAND gate included with the second sense circuit, wherein the second NAND gate receives the target clock signal and an inverted version of the reference clock signal as inputs; a third NAND gate configured to receive a corrected target clock signal and a quarter-rate clock signal; and a fourth NAND gate configured to receive the quarter-rate clock signal and the reference clock signal, wherein an output of the comparator is used to correct skew of the quarter-rate clock signal. ### Claim 18 (depends on 17) The serializer/deserializer circuit of claim 17, wherein the differential sensing circuit further comprises: a first switch between an output of the first NAND gate and a first low-pass filter included with the first sense circuit; a second switch between an output of the second NAND gate and a second low-pass filter included with the second sense circuit; a third switch between the output of the third NAND gate and the second low-pass filter; a fourth switch between the output of the fourth NAND gate and the first low-pass filter; and a controller coupled to the first, second, third, and fourth switches.