# US 11,121,810 B2 · Radar interface with enhanced frame signal

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- Number: US 11,121,810 B2
- Document ID: US11121810B2
- Status: Granted
- Kind: B2
- Application number: 16/585,811
- Filed: 2019-09-27
- Published: 2020-07-30
- Granted: 2021-09-14
- Earliest claimed: 2019-01-24
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Ljudmil Anastasov; Markus Bichl
- Web page: https://patentgrep.com/patent/US11121810B2

## CPC

- H04L 1/0063: {Single parity check}
- H04L 5/0044: {Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH}
- G01S 13/584: {adapted for simultaneous range and velocity measurements}
- H04B 7/0413: MIMO systems
- H04L 1/001: {applied to control information}
- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H04L 1/0061: {Error detection codes}
- H04L 5/0053: {Allocation of signalling, i.e. of overhead other than pilot signals}
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04L 25/4902: {Pulse width modulation; Pulse position modulation}
- G01S 7/003: {Transmission of data between radar, sonar or lidar systems and remote stations}
- G01S 13/343: {using sawtooth modulation}
- G01S 13/42: Simultaneous measurement of distance and other co-ordinates (indirect measurement G01S13/46)
- G01S 13/931: of land vehicles
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- H04B: TRANSMISSION

## Abstract

A synchronous communication interface includes at least one data channel configured to carry a data signal comprising a plurality of data units; a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information. The circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.

## Claims

### Claim 1

A synchronous communication interface, comprising:
at least one data channel configured to carry a data signal comprising a plurality of data units;
a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and
a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information,
wherein the circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states, and
wherein each period of the control signal is synchronous with a length of a corresponding data unit of the plurality of data units.

### Claim 2 (depends on 1)

The synchronous communication interface of claim 1, wherein the circuit is configured to encode the control signal by selecting a discrete duty cycle state of each duty cycle from the plurality of discrete duty cycle states based on the additional information.

### Claim 3 (depends on 1)

The synchronous communication interface of claim 1, further comprising:
a transmitter configured to synchronously transmit each data signal and the control signal, wherein the transmitter is configured to transmit one of the plurality of data units in each data signal synchronously with a period of a plurality of periods of the control signal.

### Claim 4 (depends on 1)

The synchronous communication interface of claim 1, wherein the control signal is a pulse width modulated (PWM) signal and the plurality of discrete duty cycle states are discrete pulse widths corresponding to the duty cycle of the control signal.

### Claim 5

A synchronous communication interface, comprising:
at least one data channel configured to carry a data signal comprising a plurality of data units;
a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and
a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information,
wherein the circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states,
wherein the control signal is a pulse width modulated (PWM) signal and the plurality of discrete duty cycle states are discrete pulse widths corresponding to the duty cycle of the control signal, and
wherein each first transition edge of the control signal indicates an end of a current data unit of the plurality of data units in each data signal, and each second transition edge of the control signal defines the duty cycle of the control signal corresponding to the additional information.

### Claim 6 (depends on 5)

The synchronous communication interface of claim 5, wherein the first transition edge of the control signal indicates the end of the current data unit and a start of a next data unit of the plurality of data units in each data signal.

### Claim 7 (depends on 5)

The synchronous communication interface of claim 5, wherein the circuit is configured to generate the control signal such that a period between two subsequent first transition edges is constant over a plurality of periods of the control signal and a period between two subsequent second transition edges is variable over the plurality of periods according to the plurality of discrete duty cycle states.

### Claim 8 (depends on 1)

The synchronous communication interface of claim 1, wherein the control signal is a frame signal and the plurality of data units are a plurality of data frames, wherein the frame signal indicates an end of one data frame and a beginning of a next data frame for the plurality of data frames.

### Claim 9 (depends on 1)

The synchronous communication interface of claim 1, wherein the additional information is metadata corresponding to each data signal.

### Claim 10 (depends on 1)

The synchronous communication interface of claim 1, wherein the additional information is metadata corresponding to a system status indicating a status of at least one system parameter, wherein at least a first one of the plurality of discrete duty cycle states indicates that the at least one system parameter is in a normal operating condition and at least a second one of the plurality of discrete duty cycle states indicates that the at least one system parameter is in an abnormal operating condition.

### Claim 11 (depends on 10)

The synchronous communication interface of claim 10, wherein the at least one system parameter includes at least one of a temperature, a voltage, a system clock, and a lock status of a phase-lock loop.

### Claim 12 (depends on 1)

The synchronous communication interface of claim 1, wherein the additional information indicates a data type of a corresponding data unit in each data signal, wherein at least a first one of the plurality of discrete duty cycle states indicates a first data type and at least a second one of the plurality of discrete duty cycle states indicates a second data type different from the first data type.

### Claim 13 (depends on 1)

The synchronous communication interface of claim 1, wherein the at least one data channel includes a plurality of data channels, and the additional information is a parity bit corresponding to at least two data units that are synchronous with a period of the control signal, the at least two data units being in different data signals.

### Claim 14 (depends on 13)

The synchronous communication interface of claim 13, wherein at least a first one of the plurality of discrete duty cycle states indicates a first parity bit value and at least a second one of the plurality of discrete duty cycle states indicates a second parity bit value.

### Claim 15 (depends on 1)

The synchronous communication interface of claim 1, wherein the additional information includes content of registers of an integrated circuit.

### Claim 16

A method of synchronous communication, the method comprising:
synchronously transmitting at least one data signal comprising a plurality of data units, in parallel with a control signal for the at least one data signal; and
generating the control signal that includes control information that defines each of the plurality of data units in each data signal and includes additional information, including varying a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states,
where each period of the control signal is synchronous with a length of a corresponding data unit of the plurality of data units.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
generating the control signal includes encoding the control signal by selecting a discrete duty cycle state from the plurality of discrete duty cycle states based on the additional information, and applying the duty cycle based on the selected discrete duty cycle state.

### Claim 18 (depends on 16)

The method of claim 16, wherein:
the control signal is a pulse width modulated (PWM) signal and the plurality of discrete duty cycle states are discrete pulse widths corresponding to the duty cycle,
each first transition edge of the control signal indicates an end of a current data unit of the plurality of data units in each data signal, and
each second transition edge of the control signal defines the duty cycle corresponding to the additional information.

### Claim 19

A synchronous communication interface, comprising:
at least one data channel configured to carry a data signal comprising a plurality of data units;
a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel;
a clock channel parallel to the at least one data channel and the control channel, the clock channel configured to carry a clock signal used for synchronizing communications between a transmitter and a receiver; and
a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information,
wherein the circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.

### Claim 20 (depends on 19)

The synchronous communication interface of claim 19, where each period of the control signal is synchronous with a length of a corresponding data unit.

### Claim 21 (depends on 19)

The synchronous communication interface of claim 19, wherein the control signal is a frame signal and the plurality of data units are a plurality of data frames, wherein the frame signal indicates an end of one data frame and a beginning of a next data frame for the plurality of data frames.

### Claim 22 (depends on 19)

The synchronous communication interface of claim 19, wherein:
the control signal is a pulse width modulated (PWM) signal and the plurality of discrete duty cycle states are discrete pulse widths corresponding to the duty cycle of the control signal, and
each first transition edge of the control signal indicates an end of a current data unit of the plurality of data units in each data signal, and each second transition edge of the control signal defines the duty cycle of the control signal corresponding to the additional information.
