# US 11,121,720 B2 · Analog-to-digital converter having quantization error duplicate mechanism

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- Number: US 11,121,720 B2
- Document ID: US11121720B2
- Status: Granted
- Kind: B2
- Application number: 16/934,002
- Filed: 2020-07-20
- Published: 2021-02-11
- Granted: 2021-09-14
- Earliest claimed: 2019-08-07
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Chan-Hsiang Weng; Hung-Yi Hsieh; Tzu-An Wei; Ting-Yang Wang
- Web page: https://patentgrep.com/patent/US11121720B2

## CPC

- H03M 1/802: {using capacitors, e.g. neuron-mos transistors, charge coupled devices}
- H03M 3/426: {the quantiser being a successive approximation type analogue/digital converter}
- H03M 1/0656: {in the time domain, e.g. using intended jitter as a dither signal}
- H03M 1/0854: {of quantisation noise}
- H03M 1/121: {Interleaved, i.e. using multiple converters or converter parts for one channel}
- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03M 1/662: {Multiplexed conversion systems}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

## Claims

### Claim 1

An analog-to-digital converter (ADC), comprising:
a first switched capacitor array, configured to receive an input signal and sample the input signal to generate a first sampled signal;
a second switched capacitor array, configured to sample the input signal to generate a second sampled signal and generate a first quantization error;
a third switched capacitor array, configured to sample the input signal to generate a third sampled signal and generate a second quantization error;
an integrator, coupled to the second switched capacitor array and the third switched capacitor array, configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error; and
a quantizer, coupled to the first switched capacitor array and the integrator, configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

### Claim 2 (depends on 1)

The ADC of claim 1, wherein the ADC operates alternately in a sampling phase and a quantization phase; and when the ADC operates in the sampling phase, the first switched capacitor array samples the input signal to generate the first sampled signal, one of the second switched capacitor array and the third switched capacitor array samples the input signal to generate the second/third sampled signal, and the other one of the second switched capacitor array and the third switched capacitor array sends the first/second quantization error to the integrator.

### Claim 3 (depends on 2)

The ADC of claim 2, wherein when the ADC operates in the quantization phase, the quantizer quantizes the first sampled signal by using the integrated quantization error to generate the digital output signal, and only one of the second switched capacitor array and the third switched capacitor array are controlled according to the digital output signal to generate the first/second quantization error.

### Claim 4 (depends on 1)

The ADC of claim 1, wherein the ADC operates in a first sampling phase, a first quantization phase, a second sampling phase and a second quantization phase in sequence; and when the ADC operates in the first sampling phase, the first switched capacitor array samples the input signal to generate the first sampled signal, the second switched capacitor array samples the input signal to generate the second sampled signal, and the third switched capacitor array sends the second quantization error to the integrator; when the ADC operates in the first quantization phase, the quantizer quantizes the first sampled signal by using the integrated quantization error to generate the digital output signal, and the second switched capacitor array is controlled according to the digital output signal to generate the first quantization error; when the ADC operates in the second sampling phase, the first switched capacitor array samples the input signal to generate the first sampled signal, the third switched capacitor array samples the input signal to generate the third sampled signal, and the second switched capacitor array sends the first quantization error to the integrator; and when the ADC operates in the second quantization phase, the quantizer quantizes the first sampled signal by using the integrated quantization error to generate the digital output signal, and the third switched capacitor array is controlled according to the digital output signal to generate the second quantization error.

### Claim 5 (depends on 1)

The ADC of claim 1, further comprising:
a switching circuit, configured to selectively connect the input signal to the first switched capacitor array, the second switched capacitor array and the third switched capacitor array, and selectively connect the second switched capacitor array and the third switched capacitor array to the integrator.

### Claim 6 (depends on 5)

The ADC of claim 5, wherein the switching circuit comprises:
a first switch, coupled between the input signal and the first switched capacitor array;
a second switch, coupled between the input signal and the second switched capacitor array;
a third switch, coupled between the input signal and the third switched capacitor array;
a fourth switch, coupled between second switched capacitor array and the integrator; and
a fifth switch, coupled between third switched capacitor array and the integrator.

### Claim 7 (depends on 6)

The ADC of claim 6, wherein the ADC operates in a first sampling phase, a first quantization phase, a second sampling phase and a second quantization phase in sequence; and when the ADC operates in the first sampling phase, the first switch, the second switch and the fifth switch are enabled, and the third switch and the fourth switch are disabled; when the ADC operates in the first quantization phase, the first switch, the second switch, the third switch, the fourth switch and the fifth switch are disabled; when the ADC operates in the second sampling phase, the first switch, the third switch and the fourth switch are enabled, and the second switch and the fifth switch are disabled; and when the ADC operates in the second quantization phase, the first switch, the second switch, the third switch, the fourth switch and the fifth switch are disabled.

### Claim 8 (depends on 7)

The ADC of claim 7, wherein when the ADC operates in the first sampling phase, the first switched capacitor array samples the input signal to generate the first sampled signal, the second switched capacitor array samples the input signal to generate the second sampled signal, and the third switched capacitor array sends the second quantization error to the integrator; when the ADC operates in the first quantization phase, the quantizer quantizes the first sampled signal by using the integrated quantization error to generate the digital output signal, and the second switched capacitor array is controlled according to the digital output signal to generate the first quantization error; when the ADC operates in the second sampling phase, the first switched capacitor array samples the input signal to generate the first sampled signal, the third switched capacitor array samples the input signal to generate the third sampled signal, and the second switched capacitor array sends the first quantization error to the integrator; and when the ADC operates in the second quantization phase, the quantizer quantizes the first sampled signal by using the integrated quantization error to generate the digital output signal, and the third switched capacitor array is controlled according to the digital output signal to generate the second quantization error.

### Claim 9 (depends on 1)

The ADC of claim 1, wherein a quantization error generated in the first switched capacitor array does not send to the integrator for generating the integrated quantization error.

### Claim 10 (depends on 1)

The ADC of claim 1, wherein the ADC is a successive-approximation-register (SAR) ADC.