# US 11,121,718 B1 · Multi-stage sigma-delta analog-to-digital converter with dither > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,121,718 B1 - Document ID: US11121718B1 - Status: Granted - Kind: B1 - Application number: 16/991,751 - Filed: 2020-08-12 - Granted: 2021-09-14 - Earliest claimed: 2020-08-12 - Assignees: Analog Devices International Unlimited Company - Applicants: Analog Devices International Unlimited Company - Inventors: Roberto Sergio Matteo Maurino - Web page: https://patentgrep.com/patent/US11121718B1 ## CPC - H03M 1/201: {by dithering} - H03M 3/414: {having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type} - H03M 1/0626: {by filtering} - H03M 1/0668: {the selection being based on the output of noise shaping circuits for each element} - H03M 1/122: {Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages} - H03M 1/186: {in feedforward mode, i.e. by determining the range to be selected directly from the input signal} - H03M 1/504: {using pulse width modulation} - H03M 3/33: {the dither being a random signal} - H03M 3/458: {Analogue/digital converters using delta-sigma modulation as an intermediate step} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Techniques to implement subtractive dither in a multi-stage ADC. Subtractive dither involves adding a first dither signal at a first node and adding a second dither signal at a second node (which can be the same as the first node), where the first and second dither signal combine and sum to approximately zero. By utilizing subtractive dither in a multi-stage ADC, the headroom requirements of a loop filter in a main loop of the ADC and the range requirements of a feedback DAC in the main loop can both be relaxed. ## Claims ### Claim 1 A multi-stage sigma-delta analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the multi-stage sigma-delta ADC comprising: an input summing node configured to receive and combine the analog input signal and an output of a digital-to-analog converter (DAC) circuit; a first stage ADC configured to receive the analog input signal and a first dither signal and to generate a first output to the digital-to-analog converter (DAC) circuit; and a second stage sigma-delta modulator configured to receive an output of the input summing node and a second dither signal and to generate a second output to the digital-to-analog converter (DAC) circuit, wherein the first dither signal and the second dither signal offset one another at a node coupled to an input of the DAC circuit. ### Claim 2 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the second dither signal is a noise shaped dither signal. ### Claim 3 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the second dither signal is a noise shaped dither signal that is shaped by a noise transfer function of the first stage ADC. ### Claim 4 (depends on 1) The multi-stage sigma-delta ADC of claim 1, comprising: a prefilter circuit coupled between the input and the input summing node. ### Claim 5 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the second stage sigma-delta modulator is configured in a feed-forward configuration. ### Claim 6 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the second stage sigma-delta modulator is configured in a feedback configuration. ### Claim 7 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the first stage ADC includes a first-order sigma-delta modulator, and wherein the second stage sigma-delta modulator includes a second-order sigma-delta modulator. ### Claim 8 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the first stage sigma-delta modulator includes a first ADC, wherein the second stage sigma-delta modulator includes a second ADC, wherein the first dither signal is applied to a summing node coupled to an input of the first ADC, and wherein the second dither signal is applied to a summing node coupled to an input of the second ADC. ### Claim 9 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the first dither signal and the second dither signal cancel one another at a node coupled to an input of the DAC circuit. ### Claim 10 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the sigma-delta ADC is a continuous-time ADC. ### Claim 11 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the first stage ADC includes a Nyquist-rate ADC. ### Claim 12 (depends on 1) The multi-stage sigma-delta ADC of claim 1, wherein the first stage ADC includes a sigma-delta ADC. ### Claim 13 A method of using a multi-stage sigma-delta analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the method comprising: receiving and combining the analog input signal and an output of a digital-to-analog converter (DAC) circuit at an input summing node; receiving, by a first stage ADC, the analog input signal and a first dither signal and generating a first output to the digital-to-analog converter (DAC) circuit; and receiving, by a second stage sigma-delta modulator, an output of the input summing node and a second dither signal and generating a second output to the digital-to-analog converter (DAC) circuit, wherein the first dither signal and the second dither signal offset one another at a node coupled to an input of the DAC circuit. ### Claim 14 (depends on 13) The method of claim 13, comprising: noise shaping the second dither signal by a noise transfer function of the first stage ADC. ### Claim 15 (depends on 13) The method of claim 13, comprising: prefiltering the analog input signal between the input and the input summing node. ### Claim 16 (depends on 13) The method of claim 13, comprising: in the second stage sigma-delta modulator, applying feed-forward coefficients in a feed-forward configuration. ### Claim 17 (depends on 13) The method of claim 13, comprising: in the second stage sigma-delta modulator, applying feedback coefficients in a feedback configuration. ### Claim 18 (depends on 13) The method of claim 13, wherein the first stage ADC includes a first-order sigma-delta modulator, and wherein the second stage sigma-delta modulator includes a second-order sigma-delta modulator. ### Claim 19 A multi-stage sigma-delta analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the multi-stage sigma-delta ADC comprising: means for receiving and combining the analog input signal and an output of a digital-to-analog converter (DAC) circuit; means for receiving, by a first stage ADC, the analog input signal and a first dither signal and generating a first output to the digital-to-analog converter (DAC) circuit; and means for receiving, by a second stage sigma-delta modulator, an output of an input summing node and a second dither signal and generating a second output to the digital-to-analog converter (DAC) circuit, wherein the first dither signal and the second dither signal offset one another at a node coupled to an input of the DAC circuit. ### Claim 20 (depends on 19) The multi-stage sigma-delta ADC of claim 19, the multi-stage sigma-delta ADC comprising: means for noise shaping the second dither signal by a noise transfer function of the first stage ADC.