# US 11,121,717 B2 · A/D conversion circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,121,717 B2 - Document ID: US11121717B2 - Status: Granted - Kind: B2 - Application number: 17/035,987 - Filed: 2020-09-29 - Published: 2021-04-01 - Granted: 2021-09-14 - Earliest claimed: 2019-09-30 - Assignees: Seiko Epson Corporation - Applicants: Seiko Epson Corporation - Inventors: Masayoshi Todorokihara - Web page: https://patentgrep.com/patent/US11121717B2 ## CPC - H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)} - H03M 1/56: Input signal compared with linear ramp - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal. The first time to digital converter includes a state transition section configured to start transition of a state based on the trigger signal and output state information, and a weight operation section configured to, in synchronization with the reference clock signal, perform, on a value based on the state information, weighting corresponding to time elapsing and perform a predetermined arithmetic operation to thereby calculate the first time digital value corresponding to the number of transition times of the state. ## Claims ### Claim 1 An A/D conversion circuit comprising: a comparison-reference-signal generator section configured to generate a comparison reference signal, which has a specific waveform, synchronized with a sampling clock signal; a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a first trigger signal; a first time to digital converter configured to calculate a first time digital value corresponding to a phase difference between a reference clock signal and the first trigger signal; and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value corresponding to a phase difference between the reference clock signal and a second trigger signal based on the sampling clock signal, a digital signal corresponding to the voltage of the input signal, wherein the first time to digital converter includes: a first state transition section configured to start transition of a state based on the first trigger signal and output first state information indicating the state; and a first weight operation section configured to, in synchronization with the reference clock signal, perform, on a value based on the first state information, weighting corresponding to time elapsing and perform a predetermined arithmetic operation to thereby calculate the first time digital value corresponding to a number of transition times of the state of the first state transition section. ### Claim 2 (depends on 1) The A/D conversion circuit according to claim 1, wherein the first state transition section starts the transition of the state based on the second trigger signal and outputs second state information indicating the state, and the first weight operation section performs, on a value based on the second state information, the weighting corresponding to the time elapsing and performs the arithmetic operation in synchronization with the reference clock signal to thereby calculate the second time digital value corresponding to the number of transition times of the state of the first state transition section. ### Claim 3 (depends on 1) The A/D conversion circuit according to claim 1, further comprising a second time to digital converter configured to calculate the second time digital value, wherein the second time to digital converter includes: a second state transition section configured to start transition of a state based on the second trigger signal and output second state information indicating the state; and a second weight operation section configured to, in synchronization with the reference clock signal, perform, on a value based on the second state information, weighting corresponding to time elapsing and perform the arithmetic operation to thereby calculate the second time digital value corresponding to a number of transition times of the state of the second state transition section. ### Claim 4 (depends on 3) The A/D conversion circuit according to claim 3, further comprising a third time to digital converter configured to calculate a third time digital value corresponding to a phase difference between the reference clock signal and a third trigger signal synchronized with the first trigger signal, wherein the third time to digital converter includes: a third state transition section configured to start transition of a state based on the third trigger signal and output third state information indicating the state; and a third weight operation section configured to, in synchronization with the reference clock signal, perform, on a value based on the third state information, weighing corresponding to time elapsing and perform the arithmetic operation to thereby calculate the third time digital value corresponding to a number of transition times of the state of the third state transition section, and the digital-signal generator section generates the digital signal based on the first time digital value, the second time digital value, and the third time digital value. ### Claim 5 (depends on 1) The A/D conversion circuit according to claim 1, wherein the comparison-reference-signal generator section includes an integrator circuit configured to integrate the sampling clock signal and generates the comparison reference signal based on an output signal of the integrator circuit. ### Claim 6 (depends on 5) The A/D conversion circuit according to claim 5, wherein the digital-signal generator section calculates a fluctuation amount of a time constant of the integrator circuit based on the first time digital value, the second time digital value, and a third time digital value corresponding to a phase difference between the reference clock signal and a third trigger signal synchronized with the first trigger signal and generates the digital signal compensated for the fluctuation amount. ### Claim 7 (depends on 1) The A/D conversion circuit according to claim 1, further comprising a sample hold circuit configured to sample and hold the input signal based on the sampling clock signal, wherein the comparator compares a voltage of the input signal held by the sample hold circuit and the voltage of the comparison reference signal to thereby generate the first trigger signal. ### Claim 8 (depends on 1) The A/D conversion circuit according to claim 1, wherein the sampling clock signal is synchronized with the reference clock signal. ### Claim 9 (depends on 1) The A/D conversion circuit according to claim 1, wherein the digital-signal generator section subtracts an offset value from the first time digital value and generates the digital signal based on the first time digital value from which the offset value is subtracted.