# US 11,121,715 B2 · Coarse-grain programmable routing network for logic devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,121,715 B2 - Document ID: US11121715B2 - Status: Granted - Kind: B2 - Application number: 16/777,375 - Filed: 2020-01-30 - Published: 2020-12-17 - Granted: 2021-09-14 - Earliest claimed: 2019-06-12 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Gary Wallichs; Sean Atsatt - Web page: https://patentgrep.com/patent/US11121715B2 ## CPC - H03K 19/17736: Structural details of routing resources - H03K 19/0008: {Arrangements for reducing power consumption} - H03K 19/17704: the logic functions being realised by the interconnection of rows and columns - H03K 19/1776: for memories - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure. ## Claims ### Claim 1 Circuitry, comprising: a first circuit that includes fine-grain routing wires; and a second circuit that includes a coarse-grain routing network having a plurality of channels forming a deterministic routing path, wherein a first portion of the plurality of channels is used for data payload and wherein a second portion of the plurality of channels is configured to implement an interconnect backpressure mechanism. ### Claim 2 (depends on 1) The circuitry of claim 1, wherein the first circuit is physically mounted above the second circuit. ### Claim 3 (depends on 1) The circuitry of claim 1, wherein the second portion of the plurality of channels that implements the interconnect backpressure mechanism is further configured to convey backpressure credit bits. ### Claim 4 (depends on 1) The circuitry of claim 1, wherein the second portion of the plurality of channels that implements the interconnect backpressure mechanism is further configured to convey a data valid bit. ### Claim 5 (depends on 1) The circuitry of claim 1, wherein the second portion of the plurality of channels is further configured to send timestamp information deterministically. ### Claim 6 (depends on 1) The circuitry of claim 1, wherein the second portion of the plurality of channels is further configured to support debugging operations. ### Claim 7 Circuitry, comprising: a first die that comprises fine-grain routing wires configured to provide a first level of routing granularity; and a second die that comprises a coarse-grain routing network configured to provide a second level of routing granularity that is different than the first level of routing granularity, wherein the coarse-grain routing network is further configured at run-time using control signals generated by the first die. ### Claim 8 (depends on 7) The circuitry of claim 7, wherein the first die further comprises programmable logic circuitry configured to generate the control signals. ### Claim 9 (depends on 7) The circuitry of claim 7, wherein the first die further comprises a finite state machine configured to generate the control signals. ### Claim 10 (depends on 7) The circuitry of claim 7, wherein the first die further comprises a soft processor configured to generate the control signals. ### Claim 11 (depends on 7) The circuitry of claim 7, wherein the first die further comprises a microcontroller configured to generate the control signals. ### Claim 12 (depends on 7) The circuitry of claim 7, wherein the coarse-grain routing network comprises a multiplexing circuit having a first data input configured to receive the control signals. ### Claim 13 (depends on 12) The circuitry of claim 12, wherein the multiplexing circuit has a second data input configured to receive signals from a configuration memory cell. ### Claim 14 (depends on 13) The circuitry of claim 13, wherein the multiplexing circuit has a third data input configured to receive signals from a counter. ### Claim 15 (depends on 7) The circuitry of claim 7, wherein the coarse-grain routing network comprises channels configured using a fixed bandwidth allocation. ### Claim 16 (depends on 7) The circuitry of claim 7, wherein the coarse-grain routing network comprises channels configured using a dynamically-scheduled bandwidth allocation. ### Claim 17 Circuitry, comprising: a first circuit that includes fine-grain routing wires; and a second circuit that includes a coarse-grain routing network having a plurality of channels forming a deterministic routing path. ### Claim 18 (depends on 17) The circuitry of claim 17, wherein the deterministic routing path exhibits guaranteed timing closure. ### Claim 19 (depends on 17) The circuitry of claim 17, wherein global routing for the first circuit is performed using the coarse-grain routing network in the second circuit. ### Claim 20 (depends on 17) The circuitry of claim 17, wherein the coarse-grain routing network comprises pipeline registers at fixed locations on the second circuit, and wherein register pipelining on the first circuit is adjustable.