# US 11,121,714 B2 · Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

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- Number: US 11,121,714 B2
- Document ID: US11121714B2
- Status: Granted
- Kind: B2
- Application number: 16/799,668
- Filed: 2020-02-24
- Published: 2020-08-06
- Granted: 2021-09-14
- Earliest claimed: 2017-10-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dean Gans
- Web page: https://patentgrep.com/patent/US11121714B2

## CPC

- H03K 19/018585: {programmable}
- G06F 13/4086: {Bus impedance matching, e.g. termination}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50008: {of impedance}
- H03K 19/0005: {Modifications of input or output impedance}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2207/2254: Calibration
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

## Claims

### Claim 1

A method, comprising:
operating a package comprising one or more dynamic random access memory (DRAM) dice in a mode in which calibration associated with a termination impedance (ZQ) occurs in response to a command;
determining which DRAM die or dice in the package is designated as ZQ Master; and
issuing a ZQ calibration command to the DRAM die or dice designated as ZQ Master in the package.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
reading operand 6 (OP[6]) of a mode register of one or more DRAM die or dice in the package, wherein the DRAM die or dice designated as ZQ Master is determined based at least in part on reading OP[6] of the mode register.

### Claim 3 (depends on 2)

The method of claim 2, wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
determining that the DRAM die or dice is not the ZQ Master based at least in part on reading a logic value of 0 at OP[6].

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
determining that the DRAM die or dice is the ZQ Master based at least in part on reading a logic value of 1 at OP[6].

### Claim 6 (depends on 3)

The method of claim 3, wherein a value of OP[6] has a default value of 0 to indicate that one of the DRAM die is not a ZQ Master or is set to a value of 1 to indicate that the DRAM die is a ZQ Master.

### Claim 7

An apparatus, comprising:
a memory controller configured to operate a package comprising one or more dynamic random access memory (DRAM) dice in a mode in which calibration associated with a termination impedance (ZQ) occurs in response to a command, the memory controller further configured to determine which DRAM die or dice in the package is designated as ZQ Master, and to issue a ZQ calibration command to the DRAM die or dice designated as ZQ Master in the package.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the memory controller is further configured to read operand 6 (OP[6]) of a mode register of one or more DRAM die or dice in the package, wherein the DRAM die or dice designated as ZQ Master is determined based at least in part on reading OP[6] of the mode register.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the memory controller reads a mode register comprising eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the memory controller is further configured to determine that the DRAM die or dice is not the ZQ Master based at least in part on reading a logic value of 0 at OP[6].

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the memory controller is further configured to determine that the DRAM die or dice is the ZQ Master based at least in part on reading a logic value of 1 at OP[6].

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein a value of OP[6] read by the memory controller has a default value of 0 to indicate that one of the DRAM die is not a ZQ Master or has a value of 1 to indicate that the DRAM die is a ZQ Master.

### Claim 13

A method, comprising:
in a package comprising one or more dynamic random access memory (DRAM) dice including DRAM die or dice designated as ZQ Master, operating in a mode in which calibration associated with a termination impedance (ZQ) occurs in response to a command; and
receiving a ZQ calibration command at the DRAM die or dice designated as ZQ Master in the package.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
storing information at operand 6 (OP[6]) of a mode register of one or more DRAM die or dice in the package, wherein the DRAM die or dice designated as ZQ Master is identified based at least in part on OP[6] of the mode register.

### Claim 15 (depends on 14)

The method of claim 14, wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.

### Claim 16 (depends on 14)

The method of claim 14, wherein the DRAM die or dice not designated as the ZQ Master is based at least in part on a logic value of 0 stored at OP[6].

### Claim 17 (depends on 14)

The method of claim 14, wherein the DRAM die or dice is designated the ZQ Master based at least in part on a logic value of 1 stored at OP[6].

### Claim 18

An apparatus, comprising:
a package comprising one or more dynamic random access memory (DRAM) dice including DRAM die or dice designated as ZQ Master, the package configured to operate in a mode in which calibration associated with a termination impedance (ZQ) occurs in response to a command, and further configured to receive a ZQ calibration command at the DRAM die or dice designated as ZQ Master in the package.

### Claim 19 (depends on 18)

The method of claim 18, wherein one or more DRAM die or dice in the package comprises a mode register configured to store a value at operand 6 (OP[6]), wherein the DRAM die or dice designated as ZQ Master is identified based at least in part on OP[6] of the mode register.

### Claim 20 (depends on 19)

The method of claim 19, wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.