# US 11,121,713 B1 · Boosted switch drivers for high-speed signal switching

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- Number: US 11,121,713 B1
- Document ID: US11121713B1
- Status: Granted
- Kind: B1
- Application number: 17/007,126
- Filed: 2020-08-31
- Granted: 2021-09-14
- Earliest claimed: 2020-08-14
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Scott G. Bardsley; Huseyin Dinc
- Web page: https://patentgrep.com/patent/US11121713B1

## CPC

- H03K 17/04123: {in field-effect transistor switches}
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03K 17/102: {in field-effect transistor switches}
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 19/01855: {synchronous, i.e. using clock signals}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.

## Claims

### Claim 1

A switch driver circuit, comprising:
an input, to receive an input clock signal;
an output, to provide an output clock signal;
a first transistor and a second transistor, each including a first terminal and a second terminal;
a third transistor, coupled to the first transistor in a cascode arrangement; and
a level shifter circuit, to level-shift the input clock signal to generate a level-shifted input clock signal,
wherein:
the first terminal of the first transistor is to receive a signal indicative of the input clock signal,
the first terminal of the second transistor is to receive a signal indicative of the level-shifted input clock signal,
the second terminal of the first transistor is coupled to a third terminal of the third transistor, and a second terminal of the third transistor is coupled to the output, and
the second terminal of the second transistor is coupled to the output.

### Claim 2 (depends on 1)

The switch driver circuit according to claim 1, wherein:
the input clock signal has a low voltage value and a high voltage value, and
level-shifting of the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input clock signal to generate the level-shifted input clock signal.

### Claim 3 (depends on 1)

The switch driver circuit according to claim 1, wherein the level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is to receive the signal indicative of the level-shifted input clock signal by a first capacitor electrode being coupled to the input and a second capacitor electrode being coupled to each of the voltage controller circuit and the first terminal of the second transistor.

### Claim 4 (depends on 3)

The switch driver circuit according to claim 3, wherein voltage controller circuit is to control a high voltage value of the level-shifted input clock signal.

### Claim 5 (depends on 4)

The switch driver circuit according to claim 4, wherein:
the voltage controller circuit includes a cross-coupled pair of transistors, each of which includes a first terminal, a second terminal, and a third terminal,
the first terminal of a first transistor of the cross-coupled pair of transistors is coupled to the second terminal of a second transistor of the cross-coupled pair of transistors,
the first terminal of the second transistor of the cross-coupled pair of transistors is coupled to the second terminal of the first transistor of the cross-coupled pair of transistors,
the third terminal of each of the first transistor of the cross-coupled pair of transistors and the second transistor of the cross-coupled pair of transistors is coupled to a reference voltage, and
a value of the reference voltage corresponds to the high voltage of the level-shifted input clock signal.

### Claim 6 (depends on 4)

The switch driver circuit according to claim 4, wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.

### Claim 7 (depends on 4)

The switch driver circuit according to claim 4, wherein:
the level shifter circuit is a first level shifter circuit,
the switch driver circuit further includes a second level shifter circuit, and
the second level shifter circuit is to control a low voltage level of the output clock signal.

### Claim 8 (depends on 3)

The switch driver circuit according to claim 3, wherein voltage controller circuit is to control a low voltage value of the level-shifted input clock signal.

### Claim 9 (depends on 8)

The switch driver circuit according to claim 8, wherein:
the voltage controller circuit includes a cross-coupled pair of transistors, each of which includes a first terminal, a second terminal, and a third terminal,
the first terminal of a first transistor of the cross-coupled pair of transistors is coupled to the second terminal of a second transistor of the cross-coupled pair of transistors,
the first terminal of the second transistor of the cross-coupled pair of transistors is coupled to the second terminal of the first transistor of the cross-coupled pair of transistors,
the third terminal of each of the first transistor of the cross-coupled pair of transistors and the second transistor of the cross-coupled pair of transistors is coupled to a reference voltage, and
a value of the reference voltage corresponds to the low voltage of the level-shifted input clock signal.

### Claim 10 (depends on 8)

The switch driver circuit according to claim 8, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

### Claim 11 (depends on 1)

The switch driver circuit according to claim 1, wherein each of the first transistor and the second transistor is a field-effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

### Claim 12 (depends on 4)

The switch driver circuit according to claim 4, wherein a third terminal of the second transistor is coupled to a supply voltage, and a value of the supply voltage corresponds to the high voltage of the level-shifted input clock signal.

### Claim 13 (depends on 8)

The switch driver circuit according to claim 8, wherein a third terminal of the second transistor is coupled to a supply voltage, and a value of the supply voltage corresponds to the low voltage of the level-shifted input clock signal.

### Claim 14 (depends on 8)

The switch driver circuit according to claim 8, wherein:
the level shifter circuit is a first level shifter circuit,
the switch driver circuit further includes a second level shifter circuit, and
the second level shifter circuit is to control a high voltage level of the output clock signal.

### Claim 15

A switch driver circuit, comprising:
an input, to receive an input clock signal;
an output, to provide an output clock signal;
a first transistor and a second transistor, each including a first terminal and a second terminal;
a first level shifter circuit, to level-shift the input clock signal to generate a level-shifted input clock signal; and
a second level shifter circuit;
wherein:
the first terminal of the first transistor is to receive a signal indicative of the input clock signal,
the first terminal of the second transistor is to receive a signal indicative of the level-shifted input clock signal,
the second terminal of the second transistor is coupled to the second level shifter circuit,
each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output,
the first level shifter circuit is to control a high voltage value of the level-shifted input clock signal, and
the second level shifter circuit is to control a high voltage level of the output clock signal.

### Claim 16 (depends on 15)

The switch driver circuit according to claim 15, further comprising a third transistor, coupled to the first transistor in a cascode arrangement, wherein the second terminal of the first transistor is coupled to the output by having the second terminal of the first transistor being coupled to a third terminal of the third transistor, and having a second terminal of the third transistor being coupled to the output.

### Claim 17 (depends on 15)

The switch driver circuit according to claim 15, wherein:
the input clock signal has a low voltage value and a high voltage value, and
level-shifting of the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input clock signal to generate the level-shifted input clock signal.

### Claim 18 (depends on 15)

The switch driver circuit according to claim 15, wherein the level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is to receive the signal indicative of the level-shifted input clock signal by a first capacitor electrode being coupled to the input and a second capacitor electrode being coupled to each of the voltage controller circuit and the first terminal of the second transistor.

### Claim 19 (depends on 18)

The switch driver circuit according to claim 18, wherein voltage controller circuit is to control a high voltage value of the level-shifted input clock signal.

### Claim 20 (depends on 19)

The switch driver circuit according to claim 19, wherein a third terminal of the second transistor is coupled to a supply voltage, and a value of the supply voltage corresponds to the high voltage of the level-shifted input clock signal.

### Claim 21 (depends on 19)

The switch driver circuit according to claim 19, wherein:
the voltage controller circuit includes a cross-coupled pair of transistors, each of which includes a first terminal, a second terminal, and a third terminal,
the first terminal of a first transistor of the cross-coupled pair of transistors is coupled to the second terminal of a second transistor of the cross-coupled pair of transistors,
the first terminal of the second transistor of the cross-coupled pair of transistors is coupled to the second terminal of the first transistor of the cross-coupled pair of transistors,
the third terminal of each of the first transistor of the cross-coupled pair of transistors and the second transistor of the cross-coupled pair of transistors is coupled to a reference voltage, and
a value of the reference voltage corresponds to the high voltage of the level-shifted input clock signal.

### Claim 22 (depends on 19)

The switch driver circuit according to claim 19, wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.

### Claim 23 (depends on 15)

The switch driver circuit according to claim 15, wherein each of the first transistor and the second transistor is a field-effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

### Claim 24

A switch driver circuit, comprising:
an input, to receive an input clock signal;
an output, to provide an output clock signal;
a first transistor and a second transistor, each including a first terminal and a second terminal;
a first level shifter circuit, to level-shift the input clock signal to generate a level-shifted input clock signal; and
a second level shifter circuit;
wherein:
the first terminal of the first transistor is to receive a signal indicative of the input clock signal,
the first terminal of the second transistor is to receive a signal indicative of the level-shifted input clock signal,
the second terminal of the second transistor is coupled to the second level shifter circuit,
each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output,
the first level shifter circuit is to control a low voltage value of the level-shifted input clock signal, and
the second level shifter circuit is to control a high voltage level of the output clock signal.

### Claim 25 (depends on 24)

The switch driver circuit according to claim 24, wherein the first level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is to receive the signal indicative of the level-shifted input clock signal by a first capacitor electrode being coupled to the input and a second capacitor electrode being coupled to each of the voltage controller circuit and the first terminal of the second transistor.

### Claim 26 (depends on 25)

The switch driver circuit according to claim 25, wherein:
the voltage controller circuit includes a cross-coupled pair of transistors, each of which includes a first terminal, a second terminal, and a third terminal,
the first terminal of a first transistor of the cross-coupled pair of transistors is coupled to the second terminal of a second transistor of the cross-coupled pair of transistors,
the first terminal of the second transistor of the cross-coupled pair of transistors is coupled to the second terminal of the first transistor of the cross-coupled pair of transistors,
the third terminal of each of the first transistor of the cross-coupled pair of transistors and the second transistor of the cross-coupled pair of transistors is coupled to a reference voltage, and
a value of the reference voltage corresponds to the low voltage of the level-shifted input clock signal.

### Claim 27 (depends on 24)

The switch driver circuit according to claim 24, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

### Claim 28 (depends on 24)

The switch driver circuit according to claim 24, wherein each of the first transistor and the second transistor is a field-effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

### Claim 29

An electronic component, comprising:
one or more switches; and
a switch driver circuit, to drive the one or more switches, the switch driver circuit comprising:
an input, to receive an input clock signal;
an output, to provide an output clock signal;
a first transistor and a second transistor, each including a first terminal and a second terminal;
a third transistor, coupled to the first transistor in a cascode arrangement; and
a level shifter circuit, to level-shift the input clock signal to generate a level-shifted input clock signal,
wherein:
the first terminal of the first transistor is to receive a signal indicative of the input clock signal,
the first terminal of the second transistor is to receive a signal indicative of the level-shifted input clock signal,
the second terminal of the first transistor is coupled to a third terminal of the third transistor, and a second terminal of the third transistor is coupled to the output, and
the second terminal of the second transistor is coupled to the output.

### Claim 30 (depends on 29)

The electronic component according to claim 29, wherein the electronic component is an analog-to-digital converter.

### Claim 31 (depends on 29)

The electronic component according to claim 29, wherein the electronic component is a radio frequency transceiver.

### Claim 32 (depends on 31)

The electronic component according to claim 31, wherein the electronic component further includes control logic to control operation of the switch driver circuit.

### Claim 33 (depends on 31)

The electronic component according to claim 31, wherein the electronic component further includes an analog-to-digital converter, and wherein the analog-to-digital converter includes the switch driver circuit.

### Claim 34 (depends on 29)

The electronic component according to claim 29, wherein:
the level shifter circuit is a first level shifter circuit,
the switch driver circuit further includes a second level shifter circuit,
the second terminal of the second transistor is further coupled to the second level shifter circuit,
the first level shifter circuit is to control a high voltage value of the level-shifted input clock signal, and
the second level shifter circuit is to control a high voltage level of the output clock signal.

### Claim 35 (depends on 29)

The electronic component according to claim 29, wherein:
the input clock signal has a low voltage value and a high voltage value, and
level-shifting of the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input clock signal to generate the level-shifted input clock signal.

### Claim 36

An electronic component, comprising:
one or more switches; and
a switch driver circuit, to drive the one or more switches, the switch driver circuit comprising:
an input, to receive an input clock signal;
an output, to provide an output clock signal;
a first transistor and a second transistor, each including a first terminal and a second terminal;
a first level shifter circuit, to level-shift the input clock signal to generate a level-shifted input clock signal; and
a second level shifter circuit;
wherein:
the first terminal of the first transistor is to receive a signal indicative of the input clock signal,
the first terminal of the second transistor is to receive a signal indicative of the level-shifted input clock signal,
the second terminal of the second transistor is coupled to the second level shifter circuit,
each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output,
the first level shifter circuit is to control a high voltage value of the level-shifted input clock signal, and
the second level shifter circuit is to control a high voltage level of the output clock signal.

### Claim 37 (depends on 36)

The electronic component according to claim 36, wherein the electronic component is an analog-to-digital converter.

### Claim 38 (depends on 36)

The electronic component according to claim 36, wherein the electronic component is a radio frequency transceiver.

### Claim 39 (depends on 38)

The electronic component according to claim 38, wherein the electronic component further includes control logic to control operation of the switch driver circuit.

### Claim 40 (depends on 38)

The electronic component according to claim 38, wherein the electronic component further includes an analog-to-digital converter, and wherein the analog-to-digital converter includes the switch driver circuit.

### Claim 41 (depends on 36)

The electronic component according to claim 36, wherein the switch driver circuit further includes a third transistor, coupled to the first transistor in a cascode arrangement, wherein the second terminal of the first transistor is coupled to the output by having the second terminal of the first transistor being coupled to a third terminal of the third transistor, and having a second terminal of the third transistor being coupled to the output.

### Claim 42 (depends on 36)

The electronic component according to claim 36, wherein:
the input clock signal has a low voltage value and a high voltage value, and
level-shifting of the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input clock signal to generate the level-shifted input clock signal.