# US 11,121,710 B2 · Semiconductor device

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- Number: US 11,121,710 B2
- Document ID: US11121710B2
- Status: Granted
- Kind: B2
- Application number: 17/000,708
- Filed: 2020-08-24
- Published: 2020-12-10
- Granted: 2021-09-14
- Earliest claimed: 2017-06-28
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Yasuhiro Hirashima; Masaru Koyanagi; Yutaka Takayama
- Web page: https://patentgrep.com/patent/US11121710B2

## CPC

- H03K 19/017509: {Interface arrangements}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/00: Package configurations
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

## Claims

### Claim 1

A semiconductor device comprising:
an input/output (IO) signal receiver circuit; and
a latch circuit connected to the IO signal receiver circuit,
wherein the latch circuit includes
a first inverter configured to output a first signal based on an input signal received from the IO signal receiver circuit,
a second inverter configured to output a first clock signal based on a first strobe signal,
a third inverter configured to output a second clock signal based on a second strobe signal which is an inversion signal of the first strobe signal,
a fourth inverter configured to output an inversion signal of the first signal in accordance with the first and second clock signals,
a first delay circuit configured to output a third clock signal obtained by delaying the first strobe signal relative to the first clock signal,
a second delay circuit configured to output a fourth clock signal obtained by delaying the second strobe signal relative to the second clock signal, and
a data latch circuit configured to latch an output signal of the fourth inverter in accordance with the third and fourth clock signals, and
wherein:
the data latch circuit includes a fifth inverter and a sixth inverter, the fifth inverter having an input terminal connected to an output terminal of the sixth inverter and an output terminal connected to an input terminal of the sixth inverter and the output terminal of the fourth inverter;
the output signal of the fourth inverter is latched at a non-inverted node of the data latch circuit that is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter and an inverted node of the latch circuit is connected to the output terminal of the sixth inverter and the input terminal of the fifth inverter; and
the sixth inverter is controlled in accordance with the third and fourth clock signals.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a seventh inverter having an input terminal connected to the inverted node of the data latch circuit and an output terminal connected to an output terminal of the latch circuit.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein
the first delay circuit outputs the third clock signal to a gate of a PMOS transistor of the sixth inverter, and
the second delay circuit outputs the fourth clock signal to a gate of an NMOS transistor of the sixth inverter.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
the second inverter is configured to output the first clock signal to a gate of an NMOS transistor of the fourth inverter; and
the third inverter is configured to output the second clock signal to a gate of a PMOS transistor of the fourth inverter.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein an input terminal of the first delay circuit is connected to an input terminal of the second inverter, and
an input terminal of the second delay circuit is connected to an input terminal of the third inverter.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first delay circuit includes an odd number of inverters.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein an input terminal of the first delay circuit is connected to an output terminal of the second inverter.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first delay circuit includes an even number of inverters.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first and second delay circuits include an equal number of inverters.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein
the fourth inverter discharges in accordance with the first and second clock signals, and
the sixth inverter transitions to a charge holding state in accordance with the third and fourth clock signals.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the fourth inverter completes discharging at substantially a same timing as the sixth inverter transitions to the charge holding state.